公开(公告)号：US20230309324A1

公开(公告)日：2023-09-28

申请号：US17705320

申请日：2022-03-26

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Tenko Yamashita ,  Sanjay C. Mehta ,  Junli Wang

IPC: H01L27/24

CPC classification number: H01L27/2436

Abstract: A high density memory apparatus includes a plurality of transistors vertically stacked on top of each other. The plurality of transistors share a common source structure, but each of the plurality of transistors has its own horizontal nanosheet and gate stack that are separate from respective horizontal channel structures and gate stacks of the others of the plurality of transistors. Ends of the nanosheets distal from the gate stacks are doped to act as drains for the transistors. Each of a plurality of two-terminal memory units is electrically connected to the drain end of a corresponding one of the nanosheets. Some embodiments achieve in excess of 5000 memory bits/square micrometer (μm2); in some embodiments, in excess of 6000 bits/μm2.

公开(公告)号：US20220181546A1

公开(公告)日：2022-06-09

申请号：US17114594

申请日：2020-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Injo Ok ,  RUQIANG BAO ,  Andrew Herbert Simon ,  Kevin W. Brew ,  Nicole Saulnier ,  Iqbal Rashid Saraf ,  Muthumanickam Sankarapandian ,  Sanjay C. Mehta

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor structure may include a heater surrounded by a dielectric layer, a projection liner on top of the heater, a phase change material layer above the projection liner, and a top electrode contact surrounding a top portion of the phase change material layer, The projection liner may cover a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer and the heater. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The top electrode contact may be separated from the phase change material layer by a metal liner. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

公开(公告)号：US10784371B2

公开(公告)日：2020-09-22

申请号：US16555187

申请日：2019-08-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Oleg Gluschenkov ,  Sanjay C. Mehta ,  Shogo Mochizuki ,  Alexander Reznicek

IPC: H01L31/072 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165

Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.

公开(公告)号：US10784258B2

公开(公告)日：2020-09-22

申请号：US16444755

申请日：2019-06-18

Applicant: International Business Machines Corporation

Inventor： Sanjay C. Mehta ,  Alexander Reznicek

IPC: H01L27/088 ,  H01L29/45 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/283 ,  H01L29/08 ,  H01L21/02 ,  H01L29/04 ,  H01L29/78

Abstract: A semiconductor structure includes a plurality of semiconductor material fins located on a surface of a substrate. At least one gate structure straddles over a portion of each semiconductor material fin. Unmerged source-side epitaxial semiconductor material portions are located on an exposed surfaces of each semiconductor material fin and on one side of each gate structure and unmerged drain-side epitaxial semiconductor portions are located on other exposed surfaces of each semiconductor material fin and on another side of each gate structure. An etch stop structure is located between each unmerged source-side and drain-side epitaxial semiconductor material portions. Each etch stop structure includes a bottom material portion that has a higher etch resistance in a specific etchant as compared to an upper material portion of the etch stop structure.

公开(公告)号：US20200295147A1

公开(公告)日：2020-09-17

申请号：US16351729

申请日：2019-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： RUQIANG BAO ,  HEMANTH JAGANNATHAN ,  Paul Charles Jamison ,  Choonghyun Lee ,  Sanjay C. Mehta ,  Vijay Narayanan

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/778

Abstract: A technique relates to a semiconductor device. A gate stack is formed on a fin, the gate stack being formed to have a length in a vertical direction. A gate contact is formed adjacent to the gate stack for the length of the gate stack in the vertical direction.

公开(公告)号：US10522654B2

公开(公告)日：2019-12-31

申请号：US16120870

申请日：2018-09-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/027 ,  H01L23/535 ,  H01L27/11 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.

公开(公告)号：US20190333916A1

公开(公告)日：2019-10-31

申请号：US16444755

申请日：2019-06-18

Applicant: International Business Machines Corporation

Inventor： Sanjay C. Mehta ,  Alexander Reznicek

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/283 ,  H01L29/45 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/04 ,  H01L29/08

Abstract: A semiconductor structure includes a plurality of semiconductor material fins located on a surface of a substrate. At least one gate structure straddles over a portion of each semiconductor material fin. Unmerged source-side epitaxial semiconductor material portions are located on an exposed surfaces of each semiconductor material fin and on one side of each gate structure and unmerged drain-side epitaxial semiconductor portions are located on other exposed surfaces of each semiconductor material fin and on another side of each gate structure. An etch stop structure is located between each unmerged source-side and drain-side epitaxial semiconductor material portions. Each etch stop structure includes a bottom material portion that has a higher etch resistance in a specific etchant as compared to an upper material portion of the etch stop structure.

公开(公告)号：US20180261494A1

公开(公告)日：2018-09-13

申请号：US15977437

申请日：2018-05-11

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Thomas J. Haigh ,  Juntao Li ,  Eric G. Liniger ,  Sanjay C. Mehta ,  Son V. Nguyen ,  Chanro Park ,  Tenko Yamashita

IPC: H01L21/768 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76852 ,  H01L23/528 ,  H01L23/5329 ,  H01L29/41775 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

公开(公告)号：US20180151433A1

公开(公告)日：2018-05-31

申请号：US15880059

申请日：2018-01-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/027 ,  H01L27/11 ,  H01L23/535 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US20180108661A1

公开(公告)日：2018-04-19

申请号：US15297863

申请日：2016-10-19

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Juntao Li ,  Sanjay C. Mehta ,  Robert R. Robison ,  Huimei Zhou

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L27/0924 ,  H01L21/02123 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785

Abstract: A method of forming an improved field-effect transistor device is provided. The method includes forming a tensile stressor near a first semiconductor fin. The first semiconductor fin is a fin of an n-channel field-effect transistor. The n-channel field-effect transistor is formed on a substrate. The method also includes forming a compressive stressor near a second semiconductor fin. The second semiconductor fin is a fin of a p-channel field effect transistor. The p-channel field-effect transistor is formed on the substrate. The method can also include forming neutral material over the at least one n-channel and p-channel field effect transistor. The method can also include achieving different device performance by configuring a stressor distance to fin and/or by configuring a stressor volume.