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    Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation
    55.
    发明授权
    Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation 有权
    在更换栅极形成期间保护含半导体氧化物的栅极电介质

    公开(公告)号：US09577068B2

    公开(公告)日：2017-02-21

    申请号：US15235935

    申请日：2016-08-12

    Applicant: International Business Machines Corporation

    Inventor： Gregory Costrini ,  Ravikumar Ramachandran ,  Reinaldo A. Vega ,  Richard S. Wise

    IPC: H01L27/088 ,  H01L29/51 ,  H01L21/306 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06

    CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/517 ,  H01L29/6681

    Abstract: Semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high dielectric constant (high-k) dielectric spacer can be formed to protect each semiconductor-oxide-containing gate dielectric. Formation of the high-k dielectric spacers may be performed after formation of gate cavities by removal of disposable gate structures, or prior to formation of disposable gate structures. The high-k dielectric spacers can be used as protective layers during an anisotropic etch that vertically extends the gate cavity, and can be removed after vertical extension of the gate cavities. A subset of the semiconductor-oxide-containing gate dielectrics can be removed for formation of high-k gate dielectrics for first type devices, while another subset of the semiconductor-oxide-containing gate dielectrics can be employed as gate dielectrics for second type devices. The vertical extension of the gate cavities increases channel widths in the fin field effect transistors.

    Abstract translation: 在形成一次性栅极结构之前，可以在半导体鳍片的表面上形成含半导体氧化物的栅极电介质。 可以形成高介电常数（高k）电介质间隔物以保护每个含半导体氧化物的栅极电介质。 高k电介质间隔物的形成可以在通过移除一次性栅极结构或者在形成一次性栅极结构之前形成栅极空腔之后进行。 高k电介质间隔物可以在垂直延伸栅极腔的各向异性蚀刻期间用作保护层，并且可以在栅腔的垂直延伸之后被去除。 可以去除含半导体氧化物的栅极电介质的子集，以形成用于第一类型器件的高k栅极电介质，而含半导体氧化物的栅极电介质的另一子集可用作第二类型器件的栅极电介质。 栅极腔的垂直延伸增加了鳍状场效应晶体管中的沟道宽度。

    Partial spacer for increasing self aligned contact process margins
    57.
    发明授权
    Partial spacer for increasing self aligned contact process margins 有权
    用于增加自对准接触工艺余量的部分间隔件

    公开(公告)号：US09496368B2

    公开(公告)日：2016-11-15

    申请号：US14576436

    申请日：2014-12-19

    Applicant: International Business Machines Corporation

    Inventor： Emre Alptekin ,  Ravikumar Ramachandran ,  Viraj Y. Sardesai ,  Reinaldo A. Vega

    IPC: H01L29/66 ,  H01L29/417 ,  H01L21/28 ,  H01L21/283

    CPC classification number: H01L21/76897 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/3212 ,  H01L21/76829 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

    Abstract: A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate. The semiconductor includes a first set of sidewall spacers on opposite sidewalls of the gate stack. The semiconductor includes a flowable dielectric layer on the substrate, covering at least a portion of the first set of sidewall spacers. The semiconductor includes a second set of sidewall spacers next to the first set of sidewall spacers covering an upper portion thereof, the second set of sidewall spacers are directly on top of the flowable dielectric layer. The semiconductor includes a contact next to at least one of the second set of sidewall spacers.

    Abstract translation: 提供半导体结构。 半导体在基板上包括栅极堆叠。 半导体包括在栅极叠层的相对侧壁上的第一组侧壁间隔物。 所述半导体包括在所述衬底上的可流动电介质层，其覆盖所述第一组侧壁间隔物的至少一部分。 半导体包括邻近第一组侧壁间隔件的第二组侧壁间隔件，其覆盖其上部，第二组侧壁间隔件直接位于可流动介电层的顶部上。 半导体包括邻近第二组侧壁间隔物中的至少一个的接触。

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