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    Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation
    53.
    发明授权
    Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation 有权
    在更换栅极形成期间保护含半导体氧化物的栅极电介质

    公开(公告)号：US09577068B2

    公开(公告)日：2017-02-21

    申请号：US15235935

    申请日：2016-08-12

    Applicant: International Business Machines Corporation

    Inventor： Gregory Costrini ,  Ravikumar Ramachandran ,  Reinaldo A. Vega ,  Richard S. Wise

    IPC: H01L27/088 ,  H01L29/51 ,  H01L21/306 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06

    CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/517 ,  H01L29/6681

    Abstract: Semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high dielectric constant (high-k) dielectric spacer can be formed to protect each semiconductor-oxide-containing gate dielectric. Formation of the high-k dielectric spacers may be performed after formation of gate cavities by removal of disposable gate structures, or prior to formation of disposable gate structures. The high-k dielectric spacers can be used as protective layers during an anisotropic etch that vertically extends the gate cavity, and can be removed after vertical extension of the gate cavities. A subset of the semiconductor-oxide-containing gate dielectrics can be removed for formation of high-k gate dielectrics for first type devices, while another subset of the semiconductor-oxide-containing gate dielectrics can be employed as gate dielectrics for second type devices. The vertical extension of the gate cavities increases channel widths in the fin field effect transistors.

    Abstract translation: 在形成一次性栅极结构之前，可以在半导体鳍片的表面上形成含半导体氧化物的栅极电介质。 可以形成高介电常数（高k）电介质间隔物以保护每个含半导体氧化物的栅极电介质。 高k电介质间隔物的形成可以在通过移除一次性栅极结构或者在形成一次性栅极结构之前形成栅极空腔之后进行。 高k电介质间隔物可以在垂直延伸栅极腔的各向异性蚀刻期间用作保护层，并且可以在栅腔的垂直延伸之后被去除。 可以去除含半导体氧化物的栅极电介质的子集，以形成用于第一类型器件的高k栅极电介质，而含半导体氧化物的栅极电介质的另一子集可用作第二类型器件的栅极电介质。 栅极腔的垂直延伸增加了鳍状场效应晶体管中的沟道宽度。

    Partial spacer for increasing self aligned contact process margins
    56.
    发明授权
    Partial spacer for increasing self aligned contact process margins 有权
    用于增加自对准接触工艺余量的部分间隔件

    公开(公告)号：US09496368B2

    公开(公告)日：2016-11-15

    申请号：US14576436

    申请日：2014-12-19

    Applicant: International Business Machines Corporation

    Inventor： Emre Alptekin ,  Ravikumar Ramachandran ,  Viraj Y. Sardesai ,  Reinaldo A. Vega

    IPC: H01L29/66 ,  H01L29/417 ,  H01L21/28 ,  H01L21/283

    CPC classification number: H01L21/76897 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/3212 ,  H01L21/76829 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

    Abstract: A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate. The semiconductor includes a first set of sidewall spacers on opposite sidewalls of the gate stack. The semiconductor includes a flowable dielectric layer on the substrate, covering at least a portion of the first set of sidewall spacers. The semiconductor includes a second set of sidewall spacers next to the first set of sidewall spacers covering an upper portion thereof, the second set of sidewall spacers are directly on top of the flowable dielectric layer. The semiconductor includes a contact next to at least one of the second set of sidewall spacers.

    Abstract translation: 提供半导体结构。 半导体在基板上包括栅极堆叠。 半导体包括在栅极叠层的相对侧壁上的第一组侧壁间隔物。 所述半导体包括在所述衬底上的可流动电介质层，其覆盖所述第一组侧壁间隔物的至少一部分。 半导体包括邻近第一组侧壁间隔件的第二组侧壁间隔件，其覆盖其上部，第二组侧壁间隔件直接位于可流动介电层的顶部上。 半导体包括邻近第二组侧壁间隔物中的至少一个的接触。

    Method for forming merged contact for semiconductor device
    57.
    发明授权
    Method for forming merged contact for semiconductor device 有权
    用于形成用于半导体器件的合并接触的方法

    公开(公告)号：US09431399B1

    公开(公告)日：2016-08-30

    申请号：US14969533

    申请日：2015-12-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Emre Alptekin ,  Balasubramanian Pranatharthiharan ,  Sivananda Kanakasabapathy ,  Ravikumar Ramachandran ,  Mickey H. Yu

    IPC: H01L21/336 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

    CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L29/66545

    Abstract: A method for forming a semiconductor device comprises forming a first fin and a second fin on a semiconductor substrate, forming a sacrificial gate stack over a channel region of the first fin and the second fin, depositing a layer of spacer material over the first fin and the second fin, depositing a layer of dielectric material over the layer of spacer material, removing a portion of the dielectric material to form a first cavity that exposes a portion of the first fin, epitaxially growing a first semiconductor material on the exposed portion of the first fin to form a source/drain region on the first fin, depositing a protective layer on the source/drain region on the first fin, removing a portion of the dielectric material to form a second cavity that exposes a portion of the second fin, and epitaxially growing a source/drain region on the second fin.

    Abstract translation: 一种用于形成半导体器件的方法包括在半导体衬底上形成第一鳍片和第二鳍片，在第一鳍片和第二鳍片的沟道区域上形成牺牲栅叠层，在第一鳍片之上沉积间隔物材料层， 第二鳍片，在隔离层材料层上沉积介电材料层，去除电介质材料的一部分以形成暴露第一鳍片的一部分的第一腔体，在第一鳍片的暴露部分上外延生长第一半导体材料 第一鳍片，以在第一鳍片上形成源极/漏极区域，在第一鳍片上的源极/漏极区域上沉积保护层，去除电介质材料的一部分以形成暴露第二鳍片的一部分的第二腔体， 并在第二鳍片上外延生长源/漏区域。

    Multiple thickness gate dielectrics for replacement gate field effect transistors
    59.
    发明授权
    Multiple thickness gate dielectrics for replacement gate field effect transistors 有权
    用于替换栅场效应晶体管的多厚度栅极电介质

    公开(公告)号：US09224826B2

    公开(公告)日：2015-12-29

    申请号：US14179074

    申请日：2014-02-12

    Applicant: International Business Machines Corporation

    Inventor： Unoh Kwon ,  Wing L. Lai ,  Vijay Narayanan ,  Sean M. Polvino ,  Ravikumar Ramachandran ,  Shahab Siddiqui

    IPC: H01L21/8234 ,  H01L29/51 ,  H01L29/40 ,  H01L29/423 ,  H01L27/088

    CPC classification number: H01L29/513 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545

    Abstract: After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types.

    Abstract translation: 在去除一次性栅极结构以在平坦化介电层中形成栅极空腔之后，氧化硅层被共形沉积在栅极腔中的基于氧化硅的栅极电介质部分上。 氧化硅层的一部分可以被氮化以形成氮氧化硅层。 可以使用图案化的掩模材料层来物理地暴露半导体表面从第一类型的门腔。 可以除去氧化硅层，同时在第二型栅极腔中保留下面的基于氧化硅的栅极电介质部分。 在去除第二类型栅腔中的氧化硅层时，可以通过第三型栅极腔中的图案化掩模材料层来保护硅氮氧化物层和下面的基于氧化硅的栅极电介质的堆叠。 可以在栅极腔中形成高介电常数栅极电介质层，以提供不同类型的栅极电介质。

    Strained finFET with an electrically isolated channel
    60.
    发明授权
    Strained finFET with an electrically isolated channel 有权
    具有电隔离通道的应变finFET

    公开(公告)号：US09190520B2

    公开(公告)日：2015-11-17

    申请号：US14481146

    申请日：2014-09-09

    Applicant: International Business Machines Corporation

    Inventor： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Dechao Guo ,  Myung-Hee Na ,  Ravikumar Ramachandran ,  Kern Rim ,  Huiling Shang

    IPC: H01L21/336 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

    CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    Abstract: A fin structure includes an optional doped well, a disposable single crystalline semiconductor material portion, and a top semiconductor portion formed on a substrate. A disposable gate structure straddling the fin structure is formed, and end portions of the fin structure are removed to form end cavities. Doped semiconductor material portions are formed on sides of a stack of the disposable single crystalline semiconductor material portion and a channel region including the top semiconductor portion. The disposable single crystalline semiconductor material portion may be replaced with a dielectric material portion after removal of the disposable gate structure or after formation of the stack. The gate cavity is filled with a gate dielectric and a gate electrode. The channel region is stressed by the doped semiconductor material portions, and is electrically isolated from the substrate by the dielectric material portion.

    Abstract translation: 翅片结构包括可选的掺杂阱，一次性单晶半导体材料部分和形成在衬底上的顶部半导体部分。 形成跨越翅片结构的一次性栅极结构，并且去除翅片结构的端部以形成端部空腔。 掺杂的半导体材料部分形成在一次性单晶半导体材料部分的堆叠的侧部和包括顶部半导体部分的沟道区域上。 一次性单晶半导体材料部分可以在移除一次性栅极结构之后或在堆叠形成之后用介电材料部分代替。 栅极腔填充有栅极电介质和栅电极。 沟道区域被掺杂的半导体材料部分应力，并且通过电介质材料部分与衬底电隔离。

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