公开(公告)号：US08822330B2

公开(公告)日：2014-09-02

申请号：US12906766

申请日：2010-10-18

申请人： Philippe Soussan ,  Eric Beyne ,  Philippe Muller

发明人： Philippe Soussan ,  Eric Beyne ,  Philippe Muller

IPC分类号： H01L21/4763 ,  H01L21/02 ,  H01L21/316

CPC分类号： H01L21/3167 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/31675

摘要： A method for providing an oxide layer on a semiconductor substrate is disclosed. In one aspect, the method includes obtaining a semiconductor substrate. The substrate may have a three-dimensional structure, which may comprise at least one hole. The method may also include forming an oxide layer on the substrate, for example, on the three-dimensional structure, by anodizing the substrate in an acidic electrolyte solution.

摘要翻译： 公开了一种在半导体衬底上提供氧化物层的方法。 一方面，该方法包括获得半导体衬底。 衬底可以具有三维结构，其可以包括至少一个孔。 该方法还可以包括在基板上形成氧化物层，例如在三维结构上，通过在酸性电解质溶液中阳极氧化基板。

公开(公告)号：US08647920B2

公开(公告)日：2014-02-11

申请号：US13183315

申请日：2011-07-14

申请人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Eric Beyne

发明人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Eric Beyne

IPC分类号： H01L21/00 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/302 ,  H01L21/461 ,  H01L29/06 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76898 ,  H01L21/7682 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

摘要： Ultra-low capacitance interconnect structures, preferably Through Silicon Via (TSV) interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate having a first main surface, producing at least one hollow trench-like structure therein from the first main surface, said trench-like structure surrounding an inner pillar structure of substrate material, depositing a dielectric liner which pinches off said hollow trench-like structure at the first main surface such that an airgap is created in the center of hollow trench-like structure and further creating a TSV hole and filling it at least partly with conductive material.

摘要翻译： 公开了超低电容互连结构，优选地通过硅通孔（TSV）互连和用于制造所述互连的方法。 该制造方法包括以下步骤：提供具有第一主表面的基底，从第一主表面至少产生一个中空的沟槽状结构，所述沟槽状结构围绕基底材料的内柱结构，沉积介电衬垫 其在第一主表面处夹紧所述中空沟槽状结构，使得在中空沟槽状结构的中心产生气隙，并进一步产生TSV孔并至少部分地用导电材料填充TSV孔。

公开(公告)号：US08440504B2

公开(公告)日：2013-05-14

申请号：US12864871

申请日：2008-12-29

申请人： Philippe Soussan ,  Wouter Ruythooren ,  Eric Beyne ,  Koen De Munck

发明人： Philippe Soussan ,  Wouter Ruythooren ,  Eric Beyne ,  Koen De Munck

IPC分类号： H01L21/44

CPC分类号： H01L24/90 ,  F16B5/04 ,  H01H1/04 ,  H01H11/042 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/13025 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/75 ,  H01L2224/757 ,  H01L2224/81136 ,  H01L2224/81224 ,  H01L2224/81801 ,  H01L2224/83136 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01R4/06 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： The present invention is related to a method for aligning and bonding a first element (1) and a second element (2), comprising: obtaining a first element (1) having at least one protrusion, the protrusion having a base portion (12) made of a first material and an upper portion (13) made of a second, deformable material, different from the first material; obtaining a second element (2) having a first main surface and second main surface (8) and at least one through-hole between the first and second main surface; placing the first and second element onto each other; receiving in the through-hole of the second element (2) the protrusion of the first element (1), the protrusion being arranged and constructed so as to extend from an opening of the through-hole in the first main surface to a position beyond an opening of the through-hole in the second main surface (8); deforming the deformable portion (13) of the protrusion, such that the deformed portion mechanically fixes the second element (2) on the first element (1).

摘要翻译： 本发明涉及一种用于对准和接合第一元件（1）和第二元件（2）的方法，包括：获得具有至少一个突起的第一元件（1），所述突起具有基部（12） 由与第一材料不同的第二可变形材料制成的第一材料和上部（13）制成; 获得具有第一主表面和第二主表面（8）的第二元件（2）和在第一和第二主表面之间的至少一个通孔; 将第一和第二元件彼此放置; 在所述第二元件（2）的所述通孔中容纳所述第一元件（1）的突起，所述突起被布置和构造成从所述第一主表面中的所述通孔的开口延伸到超出所述第一元件 在第二主表面（8）中的通孔的开口; 使突起的可变形部分（13）变形，使得变形部分将第二元件（2）机械地固定在第一元件（1）上。

公开(公告)号：US20120315712A1

公开(公告)日：2012-12-13

申请号：US13490828

申请日：2012-06-07

申请人： Leonardus Leunissen ,  Sandip Halder ,  Eric Beyne

发明人： Leonardus Leunissen ,  Sandip Halder ,  Eric Beyne

IPC分类号： H01L21/66

CPC分类号： H01L22/12 ,  H01L21/2885 ,  H01L21/76882 ,  H01L21/76883 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for detecting embedded voids present in a structure formed in or on a semiconductor substrate is described. The method includes performing a processing step P1 for forming the structure; measuring the mass M1 of the substrate; performing thermal treatment; measuring the mass M2 of the substrate; calculating the mass difference between the mass of the substrate measured before and after the performed thermal treatment; and deducing the presence of embedded voids in the structure by comparing the mass difference with a pre-determined value.

摘要翻译： 描述了一种用于检测存在于形成于半导体衬底中的结构中的嵌入孔的方法。 该方法包括执行用于形成结构的处理步骤P1; 测量衬底的质量M1; 进行热处理; 测量衬底的质量M2; 计算在进行的热处理之前和之后测量的基底的质量差之间的质量差; 并通过将质量差与预定值进行比较，推断结构中嵌入的空隙的存在。

公开(公告)号：US20120139127A1

公开(公告)日：2012-06-07

申请号：US13310521

申请日：2011-12-02

申请人： Eric Beyne

发明人： Eric Beyne

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/764 ,  H01L21/7682 ,  H01L23/481 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/00

摘要： A method is provided for forming at least one TSV interconnect structure surrounded by at least one isolating trench-like structure having at least one airgap. The method comprises at least the steps of providing a substrate having a first main surface and producing simultaneous at least one a TSV hole and a trench-like structure surrounding the TSV hole and separated by remaining substrate material. The method also comprises thereafter depositing a dielectric liner in order to smoothen the sidewalls of the etched TSV hole and to pinch-off the opening of the trench-like structure at the first main surface of the substrate in order to create at least one airgap in said trench-like structure and depositing a conductive material in said TSV hole in order to create a TSV interconnect. A corresponding substrate is also provided.

摘要翻译： 提供一种用于形成由至少一个具有至少一个气隙的隔离沟槽状结构包围的至少一个TSV互连结构的方法。 该方法至少包括以下步骤：提供具有第一主表面的基底，同时产生至少一个TSV孔和围绕TSV孔的沟槽状结构，并由剩余的基底材料分隔开。 该方法还包括沉积电介质衬垫以平滑所蚀刻的TSV孔的侧壁并且夹紧衬底的第一主表面处的沟槽状结构的开口，以便产生至少一个气隙 所述沟槽状结构并且在所述TSV孔中沉积导电材料以便形成TSV互连。 还提供了相应的基板。

公开(公告)号：US20110089572A1

公开(公告)日：2011-04-21

申请号：US12885311

申请日：2010-09-17

申请人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Bart Swinnen ,  Eric Beyne

发明人： Deniz Sabuncuoglu Tezcan ,  Yann Civale ,  Bart Swinnen ,  Eric Beyne

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating through substrate vias is disclosed. In one aspect, vias are etched from the backside of the substrate down to shallow trench isolation (STI) or the pre-metal dielectric stack (PMD). Extra contacts between metal 1 contact pads and the through-wafer vias are fabricated for realizing the contact between the through wafer vias and the back-end-of-line of the semiconductor chips.

摘要翻译： 公开了一种通过衬底通孔制造的方法。 在一个方面，通孔从衬底的背面蚀刻到浅沟槽隔离（STI）或预金属电介质叠层（PMD）。 制造金属1接触焊盘和贯通晶片通孔之间的额外接触，以实现贯穿晶片通孔和半导体芯片的后端行之间的接触。

公开(公告)号：US07880315B2

公开(公告)日：2011-02-01

申请号：US12463960

申请日：2009-05-11

申请人： Eric Beyne ,  Riet Labie

发明人： Eric Beyne ,  Riet Labie

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L23/40 ,  H01L23/485 ,  H01L23/488

CPC分类号： H01L24/11 ,  B81C1/00333 ,  H01L21/4846 ,  H01L21/563 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13157 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/29111 ,  H01L2224/73203 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/81948 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83194 ,  H01L2224/9211 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/00

摘要： One inventive aspect is related to a method of bonding two elements and micro-electronic devices produced according to such methods. In one aspect, a micro-electronic device includes a first and a second element, bonded together by a joining structure. The joining structure has a first micropattern portion, a second micropattern portion, and a joining portion in between the first and second micropattern portions. The first and second micropattern portions are made of cobalt. The joining portion includes intermetallic compounds of cobalt and tin (Sn).

摘要翻译： 本发明的一个方面涉及根据这种方法制造的两个元件和微电子器件的接合方法。 一方面，微电子器件包括通过接合结构结合在一起的第一和第二元件。 接合结构在第一和第二微图案部分之间具有第一微图案部分，第二微图案部分和接合部分。 第一和第二微图案部分由钴制成。 接合部分包括钴和锡（Sn）的金属间化合物。

公开(公告)号：US07795113B2

公开(公告)日：2010-09-14

申请号：US11963487

申请日：2007-12-21

申请人： Bart Swinnen ,  Eric Beyne

发明人： Bart Swinnen ,  Eric Beyne

IPC分类号： H01L21/46

CPC分类号： H01L21/6835 ,  H01L2221/6834 ,  Y10T428/24 ,  Y10T428/24628

摘要： A method is disclosed for bonding two elements by means of a bonding agent such as a glue layer, wherein the bonding agent is removable, and wherein between the bonding agent and at least one element, a sacrificial layer is applied which is selectively removable with respect to that element. According to embodiments, the elements comprise a die or a substrate bonded to a carrier wafer. The nature and type of the die or substrate and of the carrier can vary within the scope of embodiments of the invention. Also disclosed is a composite substrate obtainable by methods of the invention.

摘要翻译： 公开了一种通过诸如胶层之类的粘结剂粘接两个元件的方法，其中粘合剂是可去除的，并且其中在粘合剂和至少一个元件之间施加牺牲层，该牺牲层可相对于 到那个元素 根据实施例，元件包括结合到载体晶片的管芯或衬底。 模具或基底和载体的性质和类型可以在本发明的实施例的范围内变化。 还公开了可通过本发明的方法获得的复合基材。

公开(公告)号：US20100178810A2

公开(公告)日：2010-07-15

申请号：US12110676

申请日：2008-04-28

申请人： Arno Aarts ,  Hercules Pereira Neves ,  Chris Van Hoof ,  Eric Beyne ,  Patrick Ruther ,  Robert Puers

发明人： Arno Aarts ,  Hercules Pereira Neves ,  Chris Van Hoof ,  Eric Beyne ,  Patrick Ruther ,  Robert Puers

IPC分类号： H01R24/00 ,  H01R43/00

CPC分类号： B81C3/008 ,  A61B5/04001 ,  A61B5/0478 ,  A61B2562/125 ,  A61N1/0529 ,  A61N1/0531 ,  B81B2201/055 ,  Y10T29/49222

摘要： In the present disclosure a device for sensing and/or actuation purposes is presented in which microstructures (20) comprising shafts (2) with different functionality and dimensions can be inserted in a modular way. That way, out-of-plane connectivity, mechanical clamping between the microstructures (20) and a substrate (1) of the device, and electrical connection between electrodes (5) on the microstructures (20) and the substrate (1) can be realized. Connections to external circuitry can be realised. Microfluidic channels (10) in the microstructures (20) can be connected to external equipment. A method to fabricate and assemble the device is provided.

摘要翻译： 在本公开中，提出了用于感测和/或致动目的的装置，其中可以以模块化方式插入包括具有不同功能和尺寸的轴（2）的微结构（20）。 这样，平面外连接，微结构（20）和器件的衬底（1）之间的机械夹紧以及微结构（20）和衬底（1）上的电极（5）之间的电连接可以是 实现了 可以实现与外部电路的连接。 微结构（20）中的微流体通道（10）可以连接到外部设备。 提供了一种制造和组装该装置的方法。

公开(公告)号：US07566634B2

公开(公告)日：2009-07-28

申请号：US11234835

申请日：2005-09-23

申请人： Eric Beyne ,  Bart Swinnen ,  Serge Vanhaelemeersch

发明人： Eric Beyne ,  Bart Swinnen ,  Serge Vanhaelemeersch

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L21/3043

摘要： The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.

摘要翻译： 本发明涉及一种用于从诸如晶片或基板上的层的层叠单片化芯片的方法。 层叠层包括在衬底层上的前端（FEOL）层，衬底层具有第一表面和第二表面。 FEOL位于第一表面的顶部，并且后端（BEOL）层位于FEOL的顶部。 该方法包括通过BEOL，通过FEOL蚀刻单个沟槽并且至少部分地穿过衬底层，在设置有单个沟槽的堆叠上沉积钝化层，由此蚀刻的单个化沟槽的侧壁至少部分钝化。 执行切割，例如刀片切割，激光切割或沟槽蚀刻切割，从堆叠层释放芯片。