公开(公告)号：US3768081A

公开(公告)日：1973-10-23

申请号：US3768081D

申请日：1971-02-22

Applicant: NIPPON TELEGRAPH & TELEPHONE

Inventor： ASAOKA T ,  IEDA N

IPC: G11C11/41 ,  G11C11/24 ,  G11C11/39 ,  G11C11/40

CPC classification number: G11C11/39

Abstract: Writing and read-out are accomplished by use of minority carrier storage effect in the PN junction between the base and collector of a transistor by suitably and selectively switching potentials applied to the base, emitter and collector of the transistor. In addition the potential application across the base-emitter junction is influenced by the stored minority carriers so that the current flowing between the collector and emitter may be controlled, and a longer retention of information is permitted. A single transistor element stores a single bit of information.

Abstract translation: 通过适当且选择性地切换施加到晶体管的基极，发射极和集电极的电位，通过在晶体管的基极和集电极之间的PN结中使用少数载流子存储效应来实现写入和读出。 此外，跨基极 - 发射极结的潜在应用受到存储的少数载流子的影响，从而可以控制在集电极和发射极之间流动的电流，并且允许更长的信息保留。 单个晶体管元件存储单个位的信息。

公开(公告)号：US3699541A

公开(公告)日：1972-10-17

申请号：US3699541D

申请日：1970-12-31

Applicant: BELL TELEPHONE LABOR INC

Inventor： LYNES DENNIS JOSEPH ,  MAR JERRY

IPC: G11C11/39 ,  G11C11/40

CPC classification number: G11C11/39

Abstract: A semiconductor memory cell containing a single transistor having an uncontacted base is operated as a two-terminal device with a voltage pulse circuit coupled to the collector and a conduction detector circuit coupled to the emitter. Bit information is written into the cell by setting the potential of the base to one of two values, which represent respectively a ''''1'''' and a ''''0.'''' A ''''1'''' is written into the cell by applying a negative polarity voltage pulse to the collector of sufficient amplitude to forward bias the collector-base junction and to bias the emitter-base junction to avalanche breakdown. To read out information previously stored in the cell and to write a ''''0'''' into the cell, a positive going voltage pulse is applied to the collector.

Abstract translation: 包含具有未接触的基极的单个晶体管的半导体存储单元被操作为具有耦合到集电极的电压脉冲电路和耦合到发射极的导通检测器电路的双端器件。 通过将基数的电位设置为分别表示“1”和“0”的两个值之一，将位信息写入单元。 通过向集电极施加足够的幅度的负极性电压脉冲来将“1”写入单元，以使集电极 - 基极结偏置，并将发射极 - 基极结偏置成雪崩击穿。 为了读取先前存储在单元中的信息并将“0”写入单元，正向电压脉冲被施加到集电极。

公开(公告)号：US3680059A

公开(公告)日：1972-07-25

申请号：US3680059D

申请日：1970-09-16

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： YAMASHIFA SADAHIKO

IPC: G11C11/39 ,  H03K3/02 ,  H03K3/313 ,  G11C11/36 ,  H03B7/06

CPC classification number: G11C11/39 ,  H03K3/02 ,  H03K3/313

Abstract: A memory device comprising a circuit including in combination a gate diode and an oscillatory loop having a pulse generating diode. The oscillatory loop is adapted to produce a pulse train to be stored and to cease oscillate respectively in response to application thereto of a single and negative trigger pulse when the pulse generating diode is biased at a voltage between the oscillation starting and terminating voltages of the diode. With a reading-out pulse being applied to the loop, a single pulse or a pulse train is obtained from the stored pulse train. The pulse generating diode employed in the device is a novel having a Nu N structure.

Abstract translation: 一种存储器件，包括组合栅极二极管和具有脉冲产生二极管的振荡环路的电路。 当脉冲发生二极管偏置在二极管的振荡起始和终止电压之间的电压时，振荡回路适于响应于单个和负触发脉冲的应用而分别产生要存储的脉冲序列并停止振荡 。 利用读出脉冲施加到环路，从存储的脉冲序列获得单个脉冲或脉冲序列。 在器件中使用的脉冲发生二极管是具有nu-N结构的新颖的。

公开(公告)号：US3246300A

公开(公告)日：1966-04-12

申请号：US8947761

申请日：1961-02-15

Applicant: BUNKER RAMO

Inventor： APPLE JOSEPH S ,  SMELTZER JACK C

IPC: G11C11/39

CPC classification number: G11C11/39

公开(公告)号：US3216942A

公开(公告)日：1965-11-09

申请号：US12277361

申请日：1961-07-10

Applicant: GEN ELECTRIC

Inventor： WENTORF JR ROBERT H

IPC: C04B35/5831 ,  E04C3/09 ,  G11C11/39 ,  H01L21/00 ,  H05B33/14

CPC classification number: H05B33/145 ,  C04B35/5831 ,  E04C3/09 ,  G11C11/39 ,  H01L21/00 ,  Y10S438/932

公开(公告)号：US3093735A

公开(公告)日：1963-06-11

申请号：US458160

申请日：1960-01-22

Applicant: BLAKEWOOD CHARLES H ,  REYNOLDS DONALD C ,  WARSCHAUER DOUGLAS M

Inventor： BLAKEWOOD CHARLES H ,  REYNOLDS DONALD C ,  WARSCHAUER DOUGLAS M

IPC: G11C11/39 ,  G11C13/04 ,  H01J29/45 ,  H01J31/08 ,  H01L21/00

CPC classification number: H01J31/08 ,  G11C11/39 ,  G11C13/048 ,  H01J29/45 ,  H01L21/00

公开(公告)号：US2907000A

公开(公告)日：1959-09-29

申请号：US52663055

申请日：1955-08-05

Applicant: SPERRY RAND CORP

Inventor： LAWRENCE JR JOSEPH D

IPC: G11C11/39

CPC classification number: G11C11/39

公开(公告)号：US2873385A

公开(公告)日：1959-02-10

申请号：US53893755

申请日：1955-10-06

Applicant: BELL TELEPHONE LABOR INC

Inventor： OSTENDORF JR BERNARD

IPC: G11C11/39 ,  G11C19/28 ,  H04L25/45

CPC classification number: H04L25/45 ,  G11C11/39 ,  G11C19/28

公开(公告)号：US20230345700A1

公开(公告)日：2023-10-26

申请号：US18216359

申请日：2023-06-29

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja ,  Zvi Or-Bach

IPC: H10B12/00 ,  G11C14/00 ,  H01L29/66 ,  H01L29/788 ,  G11C11/404 ,  G11C11/39 ,  H10B12/10 ,  H01L29/78 ,  H01L29/772 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4094 ,  H01L23/528 ,  H01L29/10 ,  G11C11/4096 ,  G11C11/4099 ,  H01L29/08

CPC classification number: H10B12/20 ,  G11C14/0018 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  G11C11/404 ,  G11C11/39 ,  H10B12/10 ,  H01L29/7841 ,  H01L29/772 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4094 ,  H01L23/528 ,  H01L29/1095 ,  G11C11/4096 ,  G11C11/4099 ,  H01L29/0821 ,  H01L29/1004 ,  G11C11/4026

Abstract: An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.

公开(公告)号：US11183498B2

公开(公告)日：2021-11-23

申请号：US16844715

申请日：2020-04-09

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja ,  Zvi Or-Bach

IPC: H01L21/70 ,  H01L27/108 ,  G11C14/00 ,  H01L29/66 ,  H01L29/788 ,  G11C11/404 ,  G11C11/39 ,  H01L29/78 ,  H01L29/772 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4094 ,  H01L23/528 ,  H01L29/10 ,  G11C11/4096 ,  G11C11/4099 ,  H01L27/102 ,  H01L29/08 ,  G11C11/402 ,  G11C11/04

Abstract: An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.