公开(公告)号：US06184574B2

公开(公告)日：2001-02-06

申请号：US09417160

申请日：1999-10-12

申请人： Lucien J. Bissey

发明人： Lucien J. Bissey

IPC分类号： H01L114

CPC分类号： H01L24/49 ,  H01L23/49589 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  Y10S257/916 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A packaged integrated circuit device with a multi-level lead frame has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower lead frame and an upper lead frame, one of the lead frames being subdivided into a plurality of portions, each subdivided portion with an accessible tab for wire attachment. The planar capacitors are bonded to the bottom surface of the chip and act as a die support paddle. Each capacitor may be configured to provide the desired voltage decoupling and noise suppression for a particular portion of the integrated circuit to which it is connected. Capacitors useful for other purposes may be likewise provided in the package.

摘要翻译： 具有多级引线框架的封装集成电路器件具有多个整体电容器，其通过在下引线框架和上引线框架之间放置薄介电层而形成，其中一个引线框架被细分为多个部分 细分部分具有用于电线附接的可访问突出部。 平面电容器结合到芯片的底表面并用作模具支撑桨。 每个电容器可以被配置为为其所连接的集成电路的特定部分提供期望的电压去耦和噪声抑制。 用于其他目的的电容器也可以在包装中同样提供。

公开(公告)号：US5923999A

公开(公告)日：1999-07-13

申请号：US741159

申请日：1996-10-29

申请人： Karanam Balasubramanyam ,  Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Badih El-Kareh

发明人： Karanam Balasubramanyam ,  Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Badih El-Kareh

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/6659 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/6656 ,  H01L2924/0002 ,  Y10S257/916

摘要： A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

摘要翻译： 在其上形成有N阱的P掺杂半导体衬底上形成MOSFET器件，在N阱中形成一对隔离区，其中形成在N阱上方的栅氧化层。 FET器件在N阱内形成有源极和漏极区，以及形成在栅极氧化物层上方的与栅极和漏极区对准的栅电极。 栅电极包括一叠层。 在栅氧化层上形成多晶硅层。 在具有约5nm至约20nm的厚度的多晶硅层上形成氮化钨掺杂剂阻挡层，并且在氮化钨层上形成硅化钨层。

公开(公告)号：US5067006A

公开(公告)日：1991-11-19

申请号：US567814

申请日：1990-08-15

申请人： Nobuo Shiga

发明人： Nobuo Shiga

IPC分类号： H01L21/3205 ,  H01L23/52 ,  H01L23/64 ,  H01L27/01 ,  H01L31/10

CPC分类号： H01L23/642 ,  H01L2224/48233 ,  H01L2224/48237 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/19041 ,  Y10S257/916

摘要： The device includes an insulating substrate and first and second conducting patterns, electrically insulated from another, formed on the substrate. The second conducting pattern is connected to ground. A semiconductor chip is die-bonded to the first conducting pattern. The chip has a reception circuit, including a capacitor, formed therein, and a metal film is formed on a back surface of the chip. The capacitor includes a first terminal and a second terminal, with one of the first terminal and the second terminal being electrically connected to the first conducting pattern, such that the electric potential of the capacitor is transmitted to the metal film formed on the back surface of the chip. A buffer amplifier is interposed between the one of the first terminal and the second terminal which is electrically connected to the first conducting pattern such that the potential of the capacitor is transmitted to the metal film through the buffer amplifier. The first and second terminals constitute parallel electrode patterns forming the capacitor.

公开(公告)号：US4994936A

公开(公告)日：1991-02-19

申请号：US479075

申请日：1990-02-12

申请人： Jorge M. Hernandez

发明人： Jorge M. Hernandez

IPC分类号： H01G4/40 ,  H01L23/433 ,  H01L23/495

CPC分类号： H01G4/40 ,  H01L23/4334 ,  H01L23/49527 ,  H01L23/49555 ,  H01L23/49589 ,  H01L2224/05554 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/30107 ,  Y10S257/916

摘要： A decoupling capacitor is attached directly to an IC lead frame and thereafter encapsulated within a molded package along with an IC chip resulting in a decoupling scheme which is internal to the molded IC package. The capacitor preferably comprises a thin layer of ceramic dielectric sandwiched between top and bottom conductors. The top conductor may be attached to the die bar of the lead frame using an electrically non-conductive or conductive adhesive. Leads extending from the capacitors are attached to appropriate fingers of the lead frame by welding, soldering or the like to effect strong mechanical and electrical contact.

摘要翻译： 去耦电容器直接连接到IC引线框架，然后与IC芯片一起封装在模制封装中，导致模制IC封装内部的去耦方案。 电容器优选地包括夹在顶部和底部导体之间的薄层的陶瓷电介质。 顶部导体可以使用非导电或导电粘合剂附接到引线框架的模具棒。 从电容器延伸的引线通过焊接，焊接等附接到引线框架的适当手指，以实现强大的机械和电接触。

公开(公告)号：US4989117A

公开(公告)日：1991-01-29

申请号：US479071

申请日：1990-02-12

申请人： Jorge M. Hernandez

发明人： Jorge M. Hernandez

IPC分类号： H01L23/495

CPC分类号： H01L23/49589 ,  H01L23/49555 ,  H01L24/32 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85455 ,  H01L2224/8547 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  Y10S257/916

摘要： A decoupling scheme which is particularly well suited for use with molded integrated circuit packages incorporating lead frames is presented. In accordance with the present invention, a thin decoupling capacitor is used which is comprised of a ceramic or like substrate having printed or otherwise applied thereon conductive layers, dielectric layers (e.g., glass/ceramic dielectric paste or dielectric sol-gel) and protective layers. Mounted on this thin capacitor is an integrated circuit chip. This thin capacitor/IC chip assembly is attached directly to the IC lead frame and thereafter encapsulated within the molded package resulting in a decoupling scheme which is internal to the molded IC package. Printed conductors on the thin capacitor's ceramic substrate are attached to appropriate fingers of the lead frame by welding, soldering or the like to effect strong mechanical and electrical contact.

摘要翻译： 提出了一种特别适用于结合引线框架的模制集成电路封装的去耦方案。 根据本发明，使用薄去耦电容器，其由具有印刷或以其它方式施加在其上的陶瓷或类似衬底导电层，电介质层（例如，玻璃/陶瓷电介质糊或电介质溶胶 - 凝胶）和保护层 。 安装在该薄型电容器上的是集成电路芯片。 该薄电容器/ IC芯片组件直接附接到IC引线框架，然后封装在模制封装中，从而形成了在模制IC封装内部的去耦方案。 薄电容陶瓷基板上的印刷导体通过焊接，焊接等附接到引线框架的适当指状物，以实现强大的机械和电接触。

公开(公告)号：US4768078A

公开(公告)日：1988-08-30

申请号：US640875

申请日：1984-08-15

申请人： Shigeru Tanaka

发明人： Shigeru Tanaka

IPC分类号： H01L21/52 ,  H01L21/58 ,  H01L23/50 ,  H01L23/522 ,  H01L23/28

CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/19041 ,  Y10S257/916

摘要： A plastic-molded semiconductor device comprises a semiconductor pellet having an insulating substrate and an integrated circuit formed on the insulating substrate, and a pellet mounting member on which the semiconductor pellet is mounted. The pellet mounting member is not provided with any conductive portion at least under the center of the insulating substrate. The distance between the interconnection layer of the integrated circuit and the conductive portion of the pellet mounting member is relatively long, so the semiconductor device has a small parasitic capacitance. This results in a high speed and a low power dissipation.

摘要翻译： 一种塑料模制半导体器件包括具有绝缘衬底和形成在绝缘衬底上的集成电路的半导体芯片，以及安装半导体芯片的芯片安装构件。 颗粒安装构件至少在绝缘基板的中心以下没有设置任何导电部分。 集成电路的互连层与芯片安装部件的导电部分之间的距离相对较长，因此半导体器件具有小的寄生电容。 这导致高速度和低功耗。

公开(公告)号：US4626958A

公开(公告)日：1986-12-02

申请号：US811673

申请日：1985-12-20

申请人： Steven C. Lockard ,  Michael S. Hyslop ,  Jorge M. Hernandez

发明人： Steven C. Lockard ,  Michael S. Hyslop ,  Jorge M. Hernandez

IPC分类号： H01G2/12 ,  H01G4/228 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34 ,  H01G1/14 ,  H01L23/02

CPC分类号： H01G4/228 ,  H01G2/12 ,  H05K1/0231 ,  H05K1/18 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K3/3447 ,  Y10S257/916

摘要： High frequency noise is decoupled from power supplied to a Pin Grid Array (PGA) package by insertion of a decoupling capacitor between the PGA package and printed circuit board. The decoupling capacitor comprises a dielectric material sandwiched between a pair of conductors and having a plurality of leads extending from each conductor. In accordance with the present invention, the decoupling capacitor is individually dimensioned and configured to fit under a PGA package and correspond to the power and ground pin configuration of that PGA package.

摘要翻译： 通过在PGA封装和印刷电路板之间插入去耦电容器，高频噪声与提供给引脚栅极阵列（PGA）封装的电源脱耦。 去耦电容器包括夹在一对导体之间并具有从每个导体延伸的多个引线的电介质材料。 根据本发明，去耦电容器被独立地尺寸设计成配置在PGA封装下并对应于该PGA封装的电源和接地引脚配置。

公开(公告)号：US4443830A

公开(公告)日：1984-04-17

申请号：US480336

申请日：1983-03-30

申请人： Toshimi Kaneko ,  Yukio Hata

发明人： Toshimi Kaneko ,  Yukio Hata

IPC分类号： H01T4/10 ,  H01G2/14 ,  H01G4/40 ,  H01L27/01 ,  H01G1/11 ,  H01L27/02

CPC分类号： H01L27/01 ,  H01G4/40 ,  Y10S257/916

摘要： The disclosure is directed to an improved CR composite part provided with a discharge gap, in which discharge electrodes are provided on opposite surfaces of a substrate formed with a CR composite circuit, while an opening is provided between confronting forward ends of the discharge electrodes on the respective surfaces of the substrate, so that electrical discharge between both of the discharge electrodes is effected through the space for the opening so as to prevent adhesion of foreign matters between the discharge electrodes and also, to effectively obstruct formation of undesirable stray capacitance for stable discharging characteristics.

摘要翻译： 本发明涉及一种具有放电间隙的改进的CR复合部件，其中放电电极设置在形成有CR复合电路的基板的相对表面上，同时在放电电极的相对的前端之间设置开口 使得放电电极之间的放电通过开口的空间进行，以防止异物在放电电极之间的粘附，并且有效地阻止形成不期望的杂散电容以实现稳定的放电 特点

公开(公告)号：US4298846A

公开(公告)日：1981-11-03

申请号：US128655

申请日：1980-03-10

申请人： Yutaka Hirano ,  Nobutoshi Fukuden ,  Toshiaki Saito

发明人： Yutaka Hirano ,  Nobutoshi Fukuden ,  Toshiaki Saito

IPC分类号： H01L23/66 ,  H03H7/38

CPC分类号： H01L23/66 ,  H01L24/49 ,  H01L2223/6644 ,  H01L2224/32188 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13063 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  Y10S257/916

摘要： A high-power and high-frequency semiconductor device assembled on a base, comprising a semiconductor chip, capacitors for grounding high-frequency components, and capacitors for input impedance matching, the capacitors being arranged on a metal surface of the base.

摘要翻译： 组装在基座上的高功率和高频半导体器件，包括半导体芯片，高频部件接地电容器和用于输入阻抗匹配的电容器，电容器布置在基座的金属表面上。

公开(公告)号：US4010535A

公开(公告)日：1977-03-08

申请号：US519052

申请日：1974-10-29

申请人： Hideo Hishiki ,  Shiyousaku Yamaguchi ,  Akihisa Miyazaki

发明人： Hideo Hishiki ,  Shiyousaku Yamaguchi ,  Akihisa Miyazaki

IPC分类号： H02M3/335 ,  H02M7/10 ,  H05K13/00

CPC分类号： H02M3/335 ,  H02M7/106 ,  Y10S257/909 ,  Y10S257/916 ,  Y10T29/49117 ,  Y10T29/49137 ,  Y10T29/5317 ,  Y10T29/53265

摘要： A voltage multiplier circuit assembly circuit is fabricated by the use of an apparatus which comprises a pair of guide walls juxtaposed on a horizontal insulative support, each of the guide walls having first and second slits in opposed relation to the corresponding slits in the other. The guide walls define a first and a second area and an intermediate area therebetween. Condensers of the wafer type is placed alternately on the first and second areas with one of their electrodes facing downward. Diodes having a pair of connecting leads are placed on the intermediate area alternately with the condensers and alternately through the first and second opposed slits. Conductive cementing agent is applied between the contact points of the condensers and diodes.

摘要翻译： 通过使用包括一对并置在水平绝缘支架上的引导壁的装置来制造电压倍增器电路组合电路，每个引导壁具有与另一个相对应的狭缝相对的第一和第二狭缝。 引导壁限定第一和第二区域以及它们之间的中间区域。 晶片类型的冷凝器交替地放置在第一和第二区域上，其中一个电极面向下。 具有一对连接引线的二极管与电容器交替地放置在中间区域上，并且交替地穿过第一和第二相对的狭缝。 导电胶合剂应用于电容器和二极管的接触点之间。