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29 条记录 (耗时 0.016 秒)

    Decoupling capacitor and method of formation thereof
    2.
    发明授权
    Decoupling capacitor and method of formation thereof 失效
    去耦电容器及其形成方法

    公开(公告)号：US4594641A

    公开(公告)日：1986-06-10

    申请号：US730278

    申请日：1985-05-03

    申请人： Jorge M. Hernandez

    发明人： Jorge M. Hernandez

    IPC分类号： H01G4/12 ,  H01G4/228 ,  H01G4/30 ,  H05K1/02 ,  H05K1/18 ,  H01G1/14 ,  H01B7/00 ,  H01G7/00

    CPC分类号： H01G4/228 ,  H05K1/0231 ,  H05K1/18 ,  H05K2201/10636 ,  H05K2201/10924 ,  Y02P70/611 ,  Y10T29/435

    摘要： A decoupling capacitor is presented including a pair of conductors, each having a lead connected thereto formed from a continuous strip of electrically conductive material (lead frame), the strip having opposing planar surfaces. A pair of dummy leads, each being associated with a conductor, but isolated therefrom, is also formed from the strip. Thereafter, a strip of first insulating material is positioned across from one opposing surface of the conductive strip and a strip of second insulating material having a plurality of openings or windows therein is positioned on the other opposing surface of the conductive strip. The two insulating layers sandwiching the conductive strip are then heat tacked and hot press laminated to form a continuous strip of laminated material. The windows are positioned on the conductive strip to define access opening for the two conductors. Next, drops of solder paste are deposited on each conductor through the windows whereupon a multi-layer monolithic ceramic capacitor is placed through each window, between the two conductors and in contact with the solder paste. The multi-layer capacitor includes first and second conductive end surfaces which are electrically and mechanically bonded respectively to each conductor via the solder (after a reflow process). The multi-layer capacitor is then encapsulated and sealed by placing encapsulant material (i.e., epoxy, silicon, etc.) in the space defined by the window. Finally, the now sealed, laminated and encapsulated decoupling capacitor is severed from the lead frame. The decoupling capacitor of the present invention will thus be both hermetically sealed and automatically insertable for use in conjunction with integrated circuit DIP inserter devices.

    摘要翻译： 提供了一种去耦电容器，其包括一对导体，每个导体具有连接到其上的引线，由导电材料（引线框架）的连续条形成，所述条带具有相对的平坦表面。 每个与导体相关联但与之隔离的一对虚拟引线也由该条形成。 此后，第一绝缘材料条被定位在导电条的一个相对表面的两侧，并且其中具有多个开口或窗口的第二绝缘材料条定位在导电条的另一相对表面上。 然后将夹着导电带的两个绝缘层热固并热压层压以形成连续的层压材料条。 窗口位于导电条上，以限定两个导体的入口。 接下来，通过窗口在每个导体上沉积焊膏滴，因此多层单片陶瓷电容器通过每个窗口放置在两个导体之间并与焊膏接触。 多层电容器包括通过焊料（在回流工艺之后）分别电连接和机械地结合到每个导体的第一和第二导电端表面。 然后通过将密封剂材料（即，环氧树脂，硅等）放置在由窗户限定的空间中来封装和密封多层电容器。 最后，现在密封，层压和封装的去耦电容器从引线框架切断。 因此，本发明的去耦电容器将被密封并自动插入以与集成电路DIP插入器装置结合使用。

    Integrated circuit package having an internal cavity for incorporating decoupling capacitor
    4.
    发明授权
    Integrated circuit package having an internal cavity for incorporating decoupling capacitor 失效
    集成电路封装具有用于并入去耦电容器的内部空腔

    公开(公告)号：US5272590A

    公开(公告)日：1993-12-21

    申请号：US479074

    申请日：1990-02-12

    申请人： Jorge M. Hernandez

    发明人： Jorge M. Hernandez

    IPC分类号： H01G4/10 ,  H01G4/35 ,  H01G1/14

    CPC分类号： H01G4/35 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15312 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/30107

    摘要： A decoupling scheme is presented which is particularly well suited for use with integrated circuit packages having internal cavities for receiving an integrated circuit chip such as Pin Grid Array (PGA) packages, ceramic dual-in-line packages, ceramic flat packs and ceramic leadless chip carriers. In accordance with the present invention, a decoupling capacitor (which preferably comprises a very thin high capacitance layer made by a thick film or thin film process sandwiched between an inner and outer electrode layer) is positioned within the internal cavity of an integrated circuit package such as a PGA package and electrically connected to the IC chip within the cavity. In a particularly preferred embodiment, the decoupling capacitor has a novel configuration for improved heat transfer. This novel configuration includes a pair of parallel plate electrodes wherein the upper electrode has extended flaps which wrap around the top surface of the decoupling capacitor.

    摘要翻译： 提出了一种解耦方案，其特别适用于具有用于接收集成电路芯片的集成电路封装的集成电路封装，例如引脚格栅阵列（PGA）封装，陶瓷双列直插封装，陶瓷扁平封装和陶瓷无引线芯片 承运人 根据本发明，去耦电容器（其优选地包括由夹在内部和外部电极层之间的厚膜或薄膜工艺制成的非常薄的高电容层）位于集成电路封装的内部空腔内，例如 作为PGA封装并且电连接到腔内的IC芯片。 在特别优选的实施例中，去耦电容器具有用于改善传热的新型结构。 这种新型结构包括一对平行板电极，其中上电极具有围绕去耦电容器的顶表面缠绕的延伸片。

    Thin decoupling capacitor for mounting under integrated circuit package
    5.
    发明授权
    Thin decoupling capacitor for mounting under integrated circuit package 失效
    用于安装在集成电路封装下的薄去耦电容器

    公开(公告)号：US5034850A

    公开(公告)日：1991-07-23

    申请号：US479095

    申请日：1990-02-12

    申请人： Jorge M. Hernandez ,  Andrew B. Feinberg

    发明人： Jorge M. Hernandez ,  Andrew B. Feinberg

    IPC分类号： H01G2/06 ,  H01G4/35 ,  H05K1/02

    CPC分类号： H01G4/35 ,  H01G2/06 ,  H05K1/0231 ,  H05K2201/10515 ,  H05K2201/10689

    摘要： A rugged, highly reliable, leadless decoupling capacitor is provided which may be positioned between a circuit board and an integrated circuit package including, for example, a leaded surface mounted IC package or Pin Grid Array package. This decoupling capacitor is comprised of a rugged ceramic or like substrate having printed or otherwise applied thereon a very thin high capacitance layer made by thick or thin film processes which is sandwiched between two thin electrode layers. Conductive castellations extend from the electrode layers along the surface of the ceramic substrate for connection to the circuit board. Preferably, an electrically insulative protective layer encapsulates the capacitor. The dielectric layer preferably comprises a high dielectric glass/ceramic dielectric paste or dielectric sol-gel layer. The overall thickness of the decoupling capacitor may be less than 0.020 inch.

    摘要翻译： 提供坚固，高度可靠的无引线去耦电容器，其可以位于电路板和集成电路封装之间，该集成电路封装包括例如引线表面安装的IC封装或引脚格栅阵列封装。 该去耦电容器由具有印刷或其它方式施加在其上的由厚或薄膜工艺制成的非常薄的高电容层的坚固的陶瓷或类似衬底组成，其夹在两个薄电极层之间。 导电的cast ell从电极层沿着陶瓷基板的表面延伸以连接到电路板。 优选地，电绝缘保护层封装电容器。 电介质层优选包括高电介质玻璃/陶瓷电介质浆料或电介质溶胶 - 凝胶层。 去耦电容器的总厚度可以小于0.020英寸。

    High dielectric multilayer capacitor
    6.
    发明授权
    High dielectric multilayer capacitor 失效
    高介电多层电容器

    公开(公告)号：US4853827A

    公开(公告)日：1989-08-01

    申请号：US291520

    申请日：1988-12-29

    申请人： Jorge M. Hernandez

    发明人： Jorge M. Hernandez

    IPC分类号： H01G4/20 ,  H05K1/00 ,  H05K1/16 ,  H05K3/46

    CPC分类号： H01G4/20 ,  H05K1/162 ,  H05K1/0298 ,  H05K2201/0187 ,  H05K2201/09309 ,  H05K3/4611

    摘要： A multilayer capacitor is presented which provides high capacitance and low inductance. The capacitor comprises a plurality of conductive layers, each separated from the other and sandwiching therebetween a high capacitance flexible dielectric sheet material. The dielectric sheet material is comprised of a monolayer of multilayer or single layer high dielectric (e.g. ceramic) chips or pellets of relatively small area and thickness which are arranged in a planar array. These high dielectric constant chips are spaced apart by a small distance. The spaces between the chips are then filled with a flexible polymer/adhesive to define a cohesive sheet with the polymer binding the array of high dielectric (e.g. ceramic) chips together. Next, the opposite planar surfaces of the array (including the polymer) are electroless plated or electroded by vacuum metal deposition, or sputtering, to define opposed metallized surfaces.

    摘要翻译： 提出了一种提供高电容和低电感的层叠电容器。 电容器包括多个导电层，每个导电层彼此分离并夹在其间，具有高容量柔性电介质片材料。 介电片材料由布置成平面阵列的相对较小面积和厚度的多层或单层高电介质（例如陶瓷）芯片或小丸组成。 这些高介电常数芯片间隔开一小段距离。 然后用柔性聚合物/粘合剂填充芯片之间的空间以限定粘合片，聚合物将高电介质（例如陶瓷）芯片的阵列结合在一起。 接下来，阵列（包括聚合物）的相对的平坦表面通过真空金属沉积或溅射进行化学镀或电化，以限定相对的金属化表面。

    Multiple resonant frequency decoupling capacitor
    7.
    发明授权
    Multiple resonant frequency decoupling capacitor 失效
    多谐振频率去耦电容

    公开(公告)号：US5422782A

    公开(公告)日：1995-06-06

    申请号：US981113

    申请日：1992-11-24

    申请人： Jorge M. Hernandez ,  Daniel Douriet

    发明人： Jorge M. Hernandez ,  Daniel Douriet

    IPC分类号： H01G4/35 ,  H05K1/02 ,  H05K1/18 ,  H01G4/228 ,  H01G4/38

    CPC分类号： H01G4/35 ,  H05K1/0216 ,  H05K1/18

    摘要： A multiple resonant frequency decoupling capacitor is presented. The decoupling capacitor comprises a plurality of capacitive elements, each having a different resonant frequency to define a frequency bandwidth for noise supression. One of the capacitive elements having a resonant frequency indicative of the clock frequency of an integrated circuit being decoupled by the capacitor. Further, at least one other capacitive element having a resonant frequecny indicative of a harmonic frequency of the clock frequency.

    摘要翻译： 提出了一种多谐振频率去耦电容器。 去耦电容器包括多个电容元件，每个电容元件具有不同的谐振频率以限定用于噪声抑制的频率带宽。 具有表示集成电路的时钟频率的谐振频率的电容元件之一由电容器去耦。 此外，至少一个具有表示时钟频率的谐波频率的谐振频率的其它电容元件。

    Decoupling capacitor for leadless surface mounted chip carrier
    9.
    发明授权
    Decoupling capacitor for leadless surface mounted chip carrier 失效
    用于无引线表面安装芯片载体的去耦电容器

    公开(公告)号：US4754366A

    公开(公告)日：1988-06-28

    申请号：US27932

    申请日：1987-03-19

    申请人： Jorge M. Hernandez

    发明人： Jorge M. Hernandez

    IPC分类号： H01G2/12 ,  H01G4/228 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34 ,  H01G1/14 ,  H01G4/10 ,  H05K7/10

    CPC分类号： H01G4/228 ,  H01G2/12 ,  H05K1/0231 ,  H05K1/18 ,  H05K2201/10515 ,  H05K2201/10704 ,  H05K3/3447

    摘要： High frequency noise is decoupled from power supplied to a surface mounted integrated circuit (IC) leadless chip carrier package by installation of a surface mounted decoupling capacitor over the IC chip carrier package and printed circuit board. The decoupling capacitor comprises a dielectric material sandwiched between a pair of conductors and having a plurality of leads extending from each conductor. In accordance with the present invention, the decoupling capacitor is individually dimensioned and configured to fit over a surface mounted integrated circuit (IC) leadless chip carrier package and correspond to the power and ground pin configuration of that package.

    摘要翻译： 通过在IC芯片载体封装和印刷电路板上安装表面安装的去耦电容，高频噪声与提供给表面安装集成电路（IC）无引线芯片载体封装的电源分离。 去耦电容器包括夹在一对导体之间并具有从每个导体延伸的多个引线的电介质材料。 根据本发明，去耦电容器被独立地设计和配置成配合在表面安装的集成电路（IC）无引线芯片载体封装上并对应于该封装的电源和接地引脚配置。