公开(公告)号：US07952202B2

公开(公告)日：2011-05-31

申请号：US11847985

申请日：2007-08-30

申请人： Todd B Myers ,  Nicholas R. Watts ,  Eric C Palmer ,  Jui Min Lim

发明人： Todd B Myers ,  Nicholas R. Watts ,  Eric C Palmer ,  Jui Min Lim

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

摘要翻译： 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。 还公开了一种在其中具有一对导电路径的通孔。

公开(公告)号：US06781219B2

公开(公告)日：2004-08-24

申请号：US10229845

申请日：2002-08-27

申请人： Lucien J. Bissey

发明人： Lucien J. Bissey

IPC分类号： H01L114

CPC分类号： H01L24/49 ,  H01L23/49589 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  Y10S257/916 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A packaged integrated circuit device with a multi-level leadframe has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower leadframe and an upper leadframe, one of the leadframes being subdivided into a plurality of portions, each subdivided portion with an accessible tab for wire attachment. The planar capacitors are bonded to the bottom surface of the semiconductor chip and act as a die support paddle. Each capacitor may be configured to provide the desired voltage decoupling and noise suppression for a particular portion of the integrated circuit to which it is connected. Capacitors useful for other purposes may be likewise provided in the package.

摘要翻译： 具有多级引线框的封装集成电路器件具有多个集成电容器，其通过在下引线框架和上引线框架之间放置薄介电层而形成，其中一个引线框架被细分为多个部分，每个细分部分具有 电线附件的可访问标签。 平面电容器结合到半导体芯片的底表面并用作模具支撑桨。 每个电容器可以被配置为为其所连接的集成电路的特定部分提供期望的电压去耦和噪声抑制。 用于其他目的的电容器也可以在包装中同样提供。

公开(公告)号：US20030011050A1

公开(公告)日：2003-01-16

申请号：US10229845

申请日：2002-08-27

发明人： Lucien J. Bissey

IPC分类号： H01L023/495

CPC分类号： H01L24/49 ,  H01L23/49589 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  Y10S257/916 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A packaged integrated circuit device with a multi-level leadframe has a plurality of integral capacitors formed by placing a thin dielectric layer between a lower leadframe and an upper leadframe, one of the leadframes being subdivided into a plurality of portions, each subdivided portion with an accessible tab for wire attachment. The planar capacitors are bonded to the bottom surface of the chip and act as a die support paddle. Each capacitor may be configured to provide the desired voltage decoupling and noise suppression for a particular portion of the integrated circuit to which it is connected. Capacitors useful for other purposes may be likewise provided in the package.

公开(公告)号：US5010390A

公开(公告)日：1991-04-23

申请号：US92521

申请日：1987-09-03

申请人： Shigeru Tanaka

发明人： Shigeru Tanaka

IPC分类号： H01L21/52 ,  H01L21/58 ,  H01L23/50 ,  H01L23/522

CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/19041 ,  Y10S257/916

摘要： A plastic-molded semiconductor device comprises a semiconductor pellet having an insulating substrate and an integrated circuit formed on the insulating substrate, and a pellet mounting member on which the semiconductor pellet is mounted. The pellet mounting member is not provided with any conductive portion at least under the center of the insulating substrate. The distance between the interconnection layer of the integrated circuit and the conductive portion of the pellet mounting member is relatively long, so the semiconductor device has a small parasitic capacitance. This results in a high speed and a low power dissipation.

公开(公告)号：US4984059A

公开(公告)日：1991-01-08

申请号：US539781

申请日：1983-10-07

申请人： Akihiro Kubota ,  Rikio Sugiura ,  Tsuyoshi Aoki ,  Michio Ono

发明人： Akihiro Kubota ,  Rikio Sugiura ,  Tsuyoshi Aoki ,  Michio Ono

IPC分类号： H01L23/48 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50

CPC分类号： H01L23/49537 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49589 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  Y10S257/916

摘要： In a plastic molded semiconductor device in which inner leads overlap a semiconductor chip in a molded plastic body, the width of the chip may be close to the width of the plastic body without a decrease in the high resistance of the inner leads to the pull out thereof from the plastic body, and the layout of the inner leads may be unrestricted since the inner leads may occupy the region above the chip.

摘要翻译： 在内部引线与模制塑料体中的半导体芯片重叠的塑料模制半导体器件中，芯片的宽度可以接近塑料体的宽度，而不会使内部引线的高电阻降低到拉出 并且内引线的布局可以是不受限制的，因为内引线可能占据芯片上方的区域。

公开(公告)号：US4982311A

公开(公告)日：1991-01-01

申请号：US250549

申请日：1988-09-29

申请人： Gerard Dehaine ,  Karel Kurzweil

发明人： Gerard Dehaine ,  Karel Kurzweil

IPC分类号： H01L23/04 ,  H01L23/057 ,  H01L23/498 ,  H01L23/50 ,  H01L23/64

CPC分类号： H01L23/50 ,  H01L23/057 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/49 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19106 ,  H01L2924/30105 ,  Y10S257/916

摘要： A package (10) for very large scale integrated circuit (VLSI) includes an electrically and thermally conductive tagboard (20) carrying the chip (12); supply terminals (15a) receiving a first supply potential; an interconnect structure (16) made of ceramic which surrounds the chip (12) and carries both the signal terminals (14) of the package (10) and the supply terminals (15b) receiving a second supply potential, the interconnect structure (16) incorporating the signal and supply conductors intended for the chip (12); and a decoupling device (17) including capacitors (19) and two conductor faces (18a, 18b) connected respectively to the supply terminals (15a, 15b). The decoupling by the capicitors (19) is thus done as close as possible to the conductor faces (18a and 18b) and as close as possible to the chip (12) at the level of islets (32a, 32b).

摘要翻译： 用于超大规模集成电路（VLSI）的封装（10）包括承载芯片（12）的导电导电标签（20）。 供给端子（15a）接收第一电源电位; 由陶瓷构成的互连结构（16），其围绕所述芯片（12）并且承载所述封装（10）的信号端子（14）和接收第二电源电位的所述电源端子（15b），所述互连结构（16） 结合用于芯片（12）的信号和电源导体; 以及包括电容器（19）和分别连接到电源端子（15a，15b）的两个导体面（18a，18b）的去耦装置（17）。 因此，由钳位电路（19）进行的去耦合尽可能靠近导体面（18a和18b），并尽可能靠近胰岛（32a，32b）的芯片（12）。

公开(公告)号：US4967258A

公开(公告)日：1990-10-30

申请号：US319367

申请日：1989-03-02

申请人： Michael J. Fithian ,  James E. Foster

发明人： Michael J. Fithian ,  James E. Foster

IPC分类号： H01L23/64 ,  H01L23/66

CPC分类号： H01L23/642 ,  H01L23/66 ,  H01L2924/0002 ,  Y10S257/916

摘要： The present invention provides a structure for use in self-biasing and source bypassing a packaged, field-effect transistor (FET) having first and second leads. The structure is readily assembled and provides an excellent noise figure.

摘要翻译： 本发明提供一种用于自偏置和源极绕过具有第一和第二引线的封装的场效应晶体管（FET）的结构。 该结构易于组装并提供优异的噪音系数。

公开(公告)号：US09960079B2

公开(公告)日：2018-05-01

申请号：US13897202

申请日：2013-05-17

申请人： Intel Corporation

发明人： Todd B. Myers ,  Nicholas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

IPC分类号： H01L21/20 ,  H01L21/768 ,  H01L21/48 ,  H01L23/64 ,  H01L23/66 ,  H05K1/11 ,  H05K1/16 ,  H01L23/48 ,  H01L23/498 ,  H05K3/06 ,  H05K3/40 ,  H05K3/42

CPC分类号： H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

公开(公告)号：US6114736A

公开(公告)日：2000-09-05

申请号：US351808

申请日：1999-07-12

申请人： Karanam Balasubramanyam ,  Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Badih El-Kareh

发明人： Karanam Balasubramanyam ,  Stephen Bruce Brodsky ,  Richard Anthony Conti ,  Badih El-Kareh

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L23/283

CPC分类号： H01L29/6659 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/6656 ,  H01L2924/0002 ,  Y10S257/916

摘要： A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

摘要翻译： 在其上形成有N阱的P掺杂半导体衬底上形成MOSFET器件，在N阱中形成一对隔离区，其中形成在N阱上方的栅氧化层。 FET器件在N阱内形成有源极和漏极区，以及形成在栅极氧化物层上方的与栅极和漏极区对准的栅电极。 栅电极包括一叠层。 在栅氧化层上形成多晶硅层。 在具有约5nm至约20nm的厚度的多晶硅层上形成氮化钨掺杂剂阻挡层，并且在氮化钨层上形成硅化钨层。

公开(公告)号：USRE35109E

公开(公告)日：1995-12-05

申请号：US1613

申请日：1993-01-07

申请人： Akihiro Kubota ,  Rikio Sugiura ,  Tsuyoshi Aoki ,  Michio Ono

发明人： Akihiro Kubota ,  Rikio Sugiura ,  Tsuyoshi Aoki ,  Michio Ono

IPC分类号： H01L23/48 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H01L29/46 ,  H01L29/62 ,  H01L29/64

CPC分类号： H01L23/49537 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49589 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  Y10S257/916

摘要： In a plastic molded semiconductor device in which inner leads overlap a semiconductor chip in a molded plastic body, the width of the chip may be close to the width of the plastic body without a decrease in the high resistance of the inner leads to the pull out thereof from the plastic body, and the layout of the inner leads may be unrestricted since the inner leads may occupy the region above the chip.

摘要翻译： 在内部引线与模制塑料体中的半导体芯片重叠的塑料模制半导体器件中，芯片的宽度可以接近塑料体的宽度，而不会使内部引线的高电阻降低到拉出 并且内引线的布局可以是不受限制的，因为内引线可能占据芯片上方的区域。