公开(公告)号：US20190221558A1

公开(公告)日：2019-07-18

申请号：US16220017

申请日：2018-12-14

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Ziqi CHEN ,  Chao LI ,  Guanping WU

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/81895 ,  H01L2224/83896 ,  H01L2924/01014 ,  H01L2924/14511

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the method for forming a memory device includes the following operations. First, a plurality of first semiconductor channels can be formed over a first wafer with a peripheral device and a plurality of first via structures neighboring the plurality of first semiconductor channels. The plurality of first semiconductor channels can extend along a direction perpendicular to a surface of the first wafer. Further, a plurality of second semiconductor channels can be formed over a second wafer with a plurality of second via structures neighboring the plurality of second semiconductor channels. The plurality of second semiconductor channels can extend along a direction perpendicular to a surface of the second wafer and a peripheral via structure.

公开(公告)号：US20190214267A1

公开(公告)日：2019-07-11

申请号：US16245411

申请日：2019-01-11

Applicant: Tokyo Electron Limited

Inventor： Ryo Terashima

IPC: H01L21/311 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/28 ,  H01J37/32

CPC classification number: H01L21/31116 ,  H01J37/32449 ,  H01J2237/334 ,  H01L21/28282 ,  H01L21/31144 ,  H01L27/1157 ,  H01L27/11582

Abstract: Roughness of an end surface portion of a step shape can be decreased. An etching method includes a first etching process and a second etching process. In the first etching process, etching is performed on a processing target object, which has a silicon-containing film thereon and a photoresist formed on a surface of the silicon-containing film and which is placed in a processing vessel, to etch the silicon-containing film by using the photoresist as a mask. In the second etching process, a first processing gas containing oxygen and halogen is supplied into the processing vessel, or a third processing gas containing the oxygen is supplied into the processing vessel after a second processing gas containing the halogen is supplied into the processing vessel. The first etching process and the second etching process are repeated a multiple number of times.

公开(公告)号：US20190206726A1

公开(公告)日：2019-07-04

申请号：US16164542

申请日：2018-10-18

Applicant: Micron Technology, Inc.

Inventor： Lance Williamson ,  Adam L. Olson ,  Kaveri Jain ,  Robert Dembi ,  William R. Brown

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.

公开(公告)号：US20190198526A1

公开(公告)日：2019-06-27

申请号：US16272547

申请日：2019-02-11

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Ryan M. Meyer ,  Chet E. Carter

IPC: H01L27/11582 ,  H01L23/532 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L27/11524 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/32055 ,  H01L21/32105 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming conductively-doped semiconductor material directly above and electrically coupled to metal material. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed directly above the conductively-doped semiconductor material. Horizontally-elongated trenches are formed through the stack to the conductively-doped semiconductor material. The conductively-doped semiconductor material is oxidized through the trenches to form an oxide therefrom that is directly above the metal material. Transistor channel material is provided to extend elevationally along the alternating tiers. The wordline tiers are provided to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Charge-storage material is between the transistor channel material and the control-gate regions. Insulative charge-passage material is between the transistor channel material and the charge-storage material. A charge-blocking region is between the charge-storage material and individual of the control-gate regions.

公开(公告)号：US20190189634A1

公开(公告)日：2019-06-20

申请号：US16285829

申请日：2019-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANG-MIN CHOI ,  JU-YOUNG LIM ,  SU-JIN AHN

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/1157 ,  H01L23/528 ,  H01L27/06 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/0688 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578

Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

公开(公告)号：US20190189629A1

公开(公告)日：2019-06-20

申请号：US15843509

申请日：2017-12-15

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Justin B. Dorhout ,  Nancy M. Lomeli

IPC: H01L27/11556 ,  G11C16/08 ,  H01L27/1157 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11519 ,  H01L29/788 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7883

Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.

公开(公告)号：US20190164990A1

公开(公告)日：2019-05-30

申请号：US16126562

申请日：2018-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/36

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/36 ,  H01L29/42344

Abstract: A vertical memory device includes a gate electrode structure on a substrate, and a channel. The gate electrode structure includes gate electrodes spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The channel extends through the gate electrode structure in the vertical direction on the substrate. The channel includes a first portion having a slanted sidewall with respect to the upper surface of the substrate and a second portion contacting an upper surface of the first portion and having a slanted sidewall with respect to the upper surface of the substrate. A width of an upper surface of the second portion is less than a width of the upper surface of the first portion. An impurity region doped with carbon or p-type impurities is formed at an upper portion of the substrate. The channel contacts the impurity region.

公开(公告)号：US20190157294A1

公开(公告)日：2019-05-23

申请号：US16118647

申请日：2018-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI ,  Young-Hwan SON ,  Byung-Kwan YOU ,  Eun-Taek JUNG

IPC: H01L27/11582 ,  H01L21/768 ,  H01L23/532 ,  H01L21/56 ,  H01L21/764 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/565 ,  H01L21/764 ,  H01L21/76832 ,  H01L23/5329 ,  H01L27/1157 ,  H01L28/88 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833

Abstract: A vertical memory device includes first, second and third impurity regions sequentially stacked in a first direction substantially perpendicular to an upper surface of a substrate, a gate electrode structure including gate electrodes spaced apart from each other in the first direction on the third impurity region, a channel extending through the gate electrode structure, the second and third impurity regions, and an upper portion of the first impurity region on the substrate in the first direction, and a charge storage structure covering a portion of an outer sidewall and a lower surface of the channel. The channel directly contacts a sidewall of the second impurity region.

公开(公告)号：US20190157282A1

公开(公告)日：2019-05-23

申请号：US16012046

申请日：2018-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Jin Jung

IPC: H01L27/11556 ,  H01L27/11524 ,  G11C8/10 ,  G11C16/08 ,  H01L29/423

CPC classification number: H01L27/11556 ,  G11C7/18 ,  G11C8/10 ,  G11C16/08 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/42328

Abstract: A three-dimensional semiconductor device is provided including a gate electrode disposed on a substrate and having a pad region, a cell vertical structure passing through the gate electrode, a dummy vertical structure passing through the pad region, and a gate contact plug disposed on the pad region. The cell vertical structure includes a cell pad layer disposed on a level higher than that of the gate electrode and a cell channel layer opposing the gate electrode, the dummy vertical structure includes a buffer region formed of a material different from that of the cell pad layer and a dummy channel layer formed of a material the same as that of the cell channel layer, and at least a portion of the buffer region is located on the same plane as at least a portion of the cell pad layer.

公开(公告)号：US20190157279A1

公开(公告)日：2019-05-23

申请号：US16237913

申请日：2019-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbeom PYON ,  Kichul PARK ,  Inkwon KIM ,  Ki Hoon JANG ,  Byoungho KWON ,  Sangkyun KIM ,  Boun YOON

IPC: H01L27/112 ,  H01L23/535 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: H01L27/11286 ,  H01L21/02107 ,  H01L21/76801 ,  H01L21/76819 ,  H01L23/528 ,  H01L23/535 ,  H01L23/538 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.