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公开(公告)号：US20240136327A1
公开(公告)日：2024-04-25
申请号：US18364127
申请日：2023-08-01
发明人： AENEE JANG , SEUNGDUK BAEK
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00 , H10B80/00
CPC分类号： H01L25/0657 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/50 , H10B80/00 , H01L24/80 , H01L24/92 , H01L24/94 , H01L24/97 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/06051 , H01L2224/06132 , H01L2224/06505 , H01L2224/08145 , H01L2224/13147 , H01L2224/16145 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/49175 , H01L2224/73204 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2224/80357 , H01L2224/80379 , H01L2224/80896 , H01L2224/9212 , H01L2224/9222 , H01L2224/92247 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2924/0554 , H01L2924/0665 , H01L2924/1436
摘要： A semiconductor package includes a package substrate including a first pad; a first memory device arranged on the package substrate and including first and second semiconductor chips stacked in a vertical direction; and a first chip connecting member electrically connecting the first semiconductor chip to the package substrate. The first semiconductor chip includes a first cell structure; a first peripheral circuit structure; a first bonding pad; and a first input/output pad electrically connected to the first pad of the package substrate through the first chip connection member. The second semiconductor chip includes a second cell structure; and a second bonding pad connected to the first bonding pad. A part of the first peripheral circuit structure protrudes from a sidewall of the second semiconductor chip so as not to overlap the second semiconductor chip.
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公开(公告)号：US20240128195A1
公开(公告)日：2024-04-18
申请号：US18204970
申请日：2023-06-02
发明人： Sangwoong Lee
IPC分类号： H01L23/538 , H01L23/00 , H01L23/31 , H01L25/00 , H01L25/065 , H01L25/18 , H10B80/00
CPC分类号： H01L23/5386 , H01L23/3128 , H01L23/5383 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L25/0657 , H01L25/18 , H01L25/50 , H10B80/00 , H01L24/17 , H01L24/32 , H01L24/33 , H01L24/73 , H01L25/16 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06589 , H01L2924/014
摘要： A semiconductor package includes a first redistribution structure, a first semiconductor chip disposed on an upper surface of the first redistribution structure, an encapsulant disposed between the first redistribution structure and the first semiconductor chip, a plurality of first conductive posts electrically connecting the first redistribution structure and the first semiconductor chip with each other, and penetrating through the encapsulant in a first direction, a heat dissipation member having at least a portion that overlaps the first semiconductor chip in a second direction that is perpendicular to the first direction, and a second semiconductor chip disposed between the first redistribution structure and the heat dissipation member, and encapsulated by the encapsulant. The first semiconductor chip overlaps the plurality of first conductive posts in the first direction. The first semiconductor chip does not overlap the second semiconductor chip in the first direction.
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公开(公告)号：US20240120319A1
公开(公告)日：2024-04-11
申请号：US18376028
申请日：2023-10-03
发明人： Hyunsoo CHUNG , Younglyong KIM , Taeyoung LEE
IPC分类号： H01L25/065 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/522
CPC分类号： H01L25/0657 , H01L23/3107 , H01L23/481 , H01L23/5226 , H01L24/05 , H01L24/08 , H01L24/13 , H01L2224/05624 , H01L2224/05647 , H01L2224/08145 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147
摘要： A semiconductor package includes a first semiconductor structure including a first semiconductor layer having a first active surface and a first circuit device thereon and a first inactive surface and first bonding layer; a second semiconductor structure on the first semiconductor structure and including a second semiconductor layer having a second active surface and second circuit device thereon and a second inactive surface, a second frontside bonding layer, and a second backside bonding layer on the second inactive surface; and a third semiconductor structure on the second semiconductor structure and including a third semiconductor layer having a third active surface including a third circuit device thereon and a third inactive surface, and a third bonding layer, wherein the first bonding layer is bonded to the second frontside bonding layer, and the third bonding layer is bonded to the second backside bonding layer.
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公开(公告)号：US20240120315A1
公开(公告)日：2024-04-11
申请号：US18169579
申请日：2023-02-15
发明人： Ming-Fa Chen , Tze-Chiang Huang , Yun-Han Lee , Lee-Chung Lu
IPC分类号： H01L25/065 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/538 , H01L25/00 , H01L25/18 , H10B80/00
CPC分类号： H01L25/0652 , H01L23/3185 , H01L23/481 , H01L23/538 , H01L23/5384 , H01L24/05 , H01L24/06 , H01L24/08 , H01L25/18 , H01L25/50 , H10B80/00 , H01L24/13 , H01L2224/0401 , H01L2224/0557 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/06181 , H01L2224/08147 , H01L2224/08221 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13164
摘要： A semiconductor package includes a first semiconductor die and a second semiconductor die disposed laterally adjacent one another. The semiconductor package includes a semiconductor bridge overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. The semiconductor bridge electrically couples the first semiconductor to the second semiconductor die. The semiconductor package includes a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively. The semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die.
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公开(公告)号：US20240113066A1
公开(公告)日：2024-04-04
申请号：US18264719
申请日：2022-01-28
发明人： Takashi IMAHIGASHI
IPC分类号： H01L23/00 , H01S5/0234 , H01S5/026
CPC分类号： H01L24/73 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01S5/0234 , H01S5/0261 , H01L24/11 , H01L24/27 , H01L2224/05073 , H01L2224/05573 , H01L2224/05644 , H01L2224/1145 , H01L2224/11466 , H01L2224/1147 , H01L2224/11848 , H01L2224/13014 , H01L2224/13082 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13169 , H01L2224/14136 , H01L2224/16145 , H01L2224/2745 , H01L2224/27466 , H01L2224/2747 , H01L2224/27848 , H01L2224/29011 , H01L2224/29023 , H01L2224/29035 , H01L2224/29082 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29169 , H01L2224/32145 , H01L2224/73203 , H01L2924/01203 , H01L2924/10253 , H01L2924/10329 , H01L2924/10335 , H01L2924/12042 , H01L2924/1426
摘要： An electronic device according to the present disclosure includes a semiconductor substrate, a chip, a bump, and a sidewall portion. The bump connects a plurality of connection pads provided on the opposing main surfaces of the semiconductor substrate and the chip. The sidewall portion includes a porous metal layer and that annularly surrounds a region where a plurality of bumps is provided, and connects the semiconductor substrate and the chip. The chip has a thermal expansion coefficient different from that of the semiconductor substrate by 0.1 ppm/° C. or more. The chip is a semiconductor laser, and the semiconductor substrate includes a drive circuit that drives the semiconductor laser.
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公开(公告)号：US20240113056A1
公开(公告)日：2024-04-04
申请号：US18178229
申请日：2023-03-03
发明人： Hsing-Kuo Hsia , Chen-Hua Yu , Chih-Wei Tseng , Jui Lin Chao
IPC分类号： H01L23/00 , G02B6/12 , G02B6/13 , H01L23/498 , H10B80/00
CPC分类号： H01L24/08 , G02B6/12004 , G02B6/13 , H01L23/49833 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/80 , H10B80/00 , G02B2006/12061 , G02B2006/12121 , G02B2006/12123 , H01L24/29 , H01L24/32 , H01L24/73 , H01L2224/05022 , H01L2224/05124 , H01L2224/05562 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/08147 , H01L2224/08237 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/80357 , H01L2224/80379 , H01L2224/80895 , H01L2224/80896 , H01L2924/0504 , H01L2924/0544 , H01L2924/05494 , H01L2924/0665 , H01L2924/07025 , H01L2924/1432 , H01L2924/1433 , H01L2924/14361 , H01L2924/1437
摘要： A semiconductor package including a first interposer comprising a first substrate, first optical components over the first substrate, a first dielectric layer over the first optical components, and first conductive connectors embedded in the first dielectric layer, a photonic package bonded to a first side of the first interposer, where a first bond between the first interposer and the photonic package includes a dielectric-to-dielectric bond between a second dielectric layer on the photonic package and the first dielectric layer, and a second bond between the first interposer and the photonic package includes a metal-to-metal bond between a second conductive connector on the photonic package and a first one of the first conductive connectors and a first die bonded to the first side of the first interposer.
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公开(公告)号：US20240105652A1
公开(公告)日：2024-03-28
申请号：US18097931
申请日：2023-01-17
申请人： SK hynix Inc.
发明人： Dae Won KIM , Sung Kyu KIM
IPC分类号： H01L23/00
CPC分类号： H01L24/11 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05124 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1111 , H01L2224/11474 , H01L2224/13017 , H01L2224/13147
摘要： A method of manufacturing a semiconductor device includes forming a first photoresist layer on a substrate and forming a second photoresist layer on the first photoresist layer. The method also includes forming a first dissolvable region having a first width in the first photoresist layer and a second dissolvable region having a second width different from the first width in the second photoresist layer by radiating exposure light to some parts of the second and first photoresist layer. The method further includes forming a second opening in the second photoresist layer and a first opening in the first photoresist layer by developing the second dissolvable region and the first dissolvable region. The method additionally includes forming a conductive bump that fills the first and second openings.
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公开(公告)号：US11942025B2
公开(公告)日：2024-03-26
申请号：US17855251
申请日：2022-06-30
发明人： Jin Wan Kim , Seung Geun Lee , Sang Jo Kim , Su Jeong Kim , Young Jin Song , Byung Ju Lee
CPC分类号： G09G3/32 , G09G3/2007 , H01L25/18 , H01L27/156 , G09G2300/0452 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L2224/05573 , H01L2224/05582 , H01L2224/05611 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05687 , H01L2224/08148 , H01L2224/13082 , H01L2224/13111 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/48157 , H01L2224/73207 , H01L2224/80801 , H01L2224/81801
摘要： A display device includes a substrate, a plurality of pixel electrodes on the substrate and spaced apart from each other, a plurality of light-emitting elements on the plurality of pixel electrodes, respectively, and a common electrode layer on the plurality of light-emitting elements and to which a common voltage is applied. The plurality of light-emitting elements include a first light-emitting element that is configured to emit first light according to a first driving current and a second light-emitting element that is configured to emit second light according to a second driving current. An active layer of the first light-emitting element is the same as an active layer of the second light-emitting element.
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公开(公告)号：US20240096834A1
公开(公告)日：2024-03-21
申请号：US18126767
申请日：2023-03-27
发明人： Shih Hsuan HSU , Chan-Chung CHENG , Chun-Chen LIU , Cheng-Hung CHEN , Peng-Ren CHEN , Wen-Hao CHENG , Jong-l MOU
IPC分类号： H01L23/00
CPC分类号： H01L24/14 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/1146 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/14177 , H01L2224/16145 , H01L2224/81
摘要： A method is provided. The method includes determining a first bump map indicative of a first set of positions of bumps. The method includes determining, based upon the first bump map, a first plurality of bump densities associated with a plurality of regions of the first bump map. The method includes smoothing the first plurality of bump densities to determine a second plurality of bump densities associated with the plurality of regions of the first bump map. The method includes determining, based upon the second plurality of bump densities, a second bump map indicative of the first set of positions of the bumps and a set of sizes of the bumps.
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公开(公告)号：US20240088074A1
公开(公告)日：2024-03-14
申请号：US18184480
申请日：2023-03-15
发明人： Chia-Feng Cheng , Kang-Yi Lien , Chia-Ping Lai
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L24/03 , H01L28/91 , H01L24/11 , H01L24/13 , H01L2224/02206 , H01L2224/02215 , H01L2224/03462 , H01L2224/03827 , H01L2224/0391 , H01L2224/03912 , H01L2224/05018 , H01L2224/05019 , H01L2224/05022 , H01L2224/05027 , H01L2224/05084 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05558 , H01L2224/05572 , H01L2224/05647 , H01L2224/11462 , H01L2224/11849 , H01L2224/13021 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2924/0132 , H01L2924/0133 , H01L2924/04941 , H01L2924/04953 , H01L2924/0496 , H01L2924/0504
摘要： Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a metal feature in a dielectric layer, a passivation structure over the dielectric layer and the metal feature, a contact pad over the passivation structure, and a plurality of contact vias extending through the passivation structure and in contact with the metal feature and the contact pad.
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