公开(公告)号：US20180210652A1

公开(公告)日：2018-07-26

申请号：US15456584

申请日：2017-03-13

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Ming Chen ,  An-Chung Chen ,  Kuen-Chih Lin

IPC: G06F3/06

CPC classification number: G06F1/08 ,  G06F13/16

Abstract: An exemplary embodiment of the present disclosure provides a reference clock signal generation method for a memory storage device. The method includes: receiving a first type signal from a host system; generating a first control parameter according to a frequency of the first type signal; receiving a second type signal from the host system after the first type signal is received; generating a second control parameter according to a frequency of the second type signal; and generating a reference clock signal meeting a first condition according to the second control parameter. Therefore, an efficiency of generating the reference clock signal can be improved.

公开(公告)号：US20180196917A1

公开(公告)日：2018-07-12

申请号：US15916054

申请日：2018-03-08

Applicant: Edico Genome Corporation

Inventor： Pieter van Rooyen ,  Robert J. McMillen ,  Michael Ruehle

IPC: G06F19/28 ,  G06F19/22

CPC classification number: G06F19/22 ,  G06F13/16 ,  G06F13/4068 ,  G06F13/4265 ,  G06F19/24 ,  G06F19/28 ,  H01L21/768 ,  H01L21/76886 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/118 ,  H01L27/11807 ,  H01L2027/11838 ,  H01L2027/11883 ,  H03K19/17736

Abstract: A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a structured ASIC formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the structured ASIC connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.

公开(公告)号：US10019406B2

公开(公告)日：2018-07-10

申请号：US15803639

申请日：2017-11-03

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Helena Deirdre O'Shea ,  ZhenQi Chen ,  Wolfgang Roethig

IPC: G06F13/38 ,  G06F13/42 ,  G06F21/85 ,  G06F13/40 ,  G06F13/364

CPC classification number: G06F13/4286 ,  G06F13/102 ,  G06F13/16 ,  G06F13/28 ,  G06F13/364 ,  G06F13/4022 ,  G06F21/85

Abstract: Methods and apparatuses are described that facilitate data communication between a first slave device and a second slave device across a serial bus interface. In one configuration, a master device receives, from a first slave device, a request to send a masked-write datagram to a second slave device via a bus, wherein the masked-write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device. The masked-write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and a data field providing a value of the at least one bit to be changed in the RFFE register. The master device detects whether the first slave device is authorized to send the masked-write datagram to the second slave device and permits the first slave device to send the masked-write datagram to the second slave device if authorization is detected.

公开(公告)号：US10014072B2

公开(公告)日：2018-07-03

申请号：US15335783

申请日：2016-10-27

Applicant: FUJITSU LIMITED

Inventor： Hiroyuki Nishimura ,  Yukio Suda ,  Satoshi Nemoto

IPC: H03K7/08 ,  G11C7/10 ,  G11C29/12 ,  G11C7/22 ,  G06F13/16 ,  G11C29/02 ,  G11C29/50 ,  G11C29/04 ,  G11C29/36

CPC classification number: G11C29/12 ,  G06F13/16 ,  G11C7/10 ,  G11C7/222 ,  G11C29/022 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/36 ,  G11C29/50012 ,  G11C2029/0409

Abstract: A diagnosis method executed by a processor includes receiving signal data at a timing of a first clock signal; setting a diagnosis period to perform a diagnosis of a memory with a predetermined period; executing a write operation and a read operation of the signal data on the memory at a timing of a second clock signal that is higher in rate than the first clock signal within the diagnosis period; executing at least one of operations included in the diagnosis of the memory using diagnosis data at a timing of the second clock signal during a period responsive to a difference between a number of first clock pulses of the first clock signal within the diagnosis period and a number of second clock pulses of the second clock signal within the diagnosis period; and diagnosing the memory by repeating the diagnosis period by a plurality of times.

公开(公告)号：US10007292B2

公开(公告)日：2018-06-26

申请号：US15170615

申请日：2016-06-01

Applicant: QUALCOMM Incorporated

Inventor： Lucille Garwood Sylvester ,  Navid Farazmand ,  Brian Salsbery ,  Jeremy Gebben

IPC: G06F1/00 ,  G06F1/08 ,  G06F13/16 ,  G06T1/20

CPC classification number: G06F1/08 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3253 ,  G06F1/3275 ,  G06F13/16 ,  G06T1/20 ,  G06T2200/28 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Example implementations and techniques are described in which a processor uses a dynamic adjustment algorithm, including algorithms based on performance and energy models, to readjust frequency settings for a graphics processing unit (GPU), and independently for a system memory or for a system memory bus, to an optimal level for meeting sustained performance requirements with the low level of power consumption.

公开(公告)号：US20180173429A1

公开(公告)日：2018-06-21

申请号：US15659863

申请日：2017-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James J. Bonanno ,  Michael J. Cadigan, JR. ,  Adam B. Collura ,  Daniel Lipetz ,  Patrick J. Meaney ,  Craig R. Walters

IPC: G06F3/06 ,  G11C11/4091 ,  G11C11/406

CPC classification number: G06F3/0611 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/16 ,  G11C5/04 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227

Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.

公开(公告)号：US10002246B2

公开(公告)日：2018-06-19

申请号：US14949306

申请日：2015-11-23

Applicant: NXP B.V.

Inventor： Mark Buer ,  Theodore Trost ,  Jacob Mendel

IPC: G06F3/00 ,  G06F13/12 ,  G06F13/00 ,  G06F21/53 ,  G06F21/76 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F21/60

CPC classification number: G06F21/53 ,  G06F12/1408 ,  G06F13/16 ,  G06F13/4068 ,  G06F13/4282 ,  G06F21/602 ,  G06F21/76 ,  G06F2212/1052 ,  G06F2221/034 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods are provided that allow a secure processing system (SPS) to be implemented as a hard macro, thereby isolating the SPS from a peripheral processing system (PPS). The SPS and the PPS, combination, may form a secure element that can be used in conjunction with a host device and a connectivity device to allow the host device to engage in secure transactions, such as mobile payment over a near field communications (NFC) connection. As a result of the SPS being implemented as a hard macro isolated from the PPS, the SPS may be certified once, and re-used in other host devices without necessitating re-certification.

公开(公告)号：US20180143769A1

公开(公告)日：2018-05-24

申请号：US15572971

申请日：2015-07-31

Applicant: Luis Miguel VAQUERO GONZALEZ ,  Suksant SAE LOR ,  Hewlett Packard Enterprise Development LP

Inventor： Luis Miguel Vaquero Gonzalez ,  Suksant Sae Lor

IPC: G06F3/06

CPC classification number: G06F3/0607 ,  G06F3/0635 ,  G06F3/0685 ,  G06F13/16

Abstract: The present disclosure discloses a method comprising: determining a root router memory module of a memory system comprising a plurality of router memory module, each router memory module comprising at least one port to connect the router memory module to at least another router memory module, for each router memory module apart from the root router memory module, identifying a loop-free path from the router memory module to the root router memory module, creating a logical tree using the loop-free paths determined.

公开(公告)号：US20180137050A1

公开(公告)日：2018-05-17

申请号：US15808718

申请日：2017-11-09

Applicant: QUALCOMM Incorporated

Inventor： Nikhil JAIN ,  Ankit SHAMBHU ,  Shyam Bahadur RAGHUBANSHI ,  Umesh RAO

IPC: G06F12/04 ,  G06F1/32 ,  G06F12/1009

CPC classification number: G06F12/04 ,  G06F1/3275 ,  G06F12/0207 ,  G06F12/1009 ,  G06F13/16 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/65 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  Y02D10/13

Abstract: Systems and method are directed to reducing power consumption and/or improving performance of a processing system comprising a processor subsystem and a memory subsystem. A variable length column command is used in place of a plurality of column commands directed to a same page of a memory bank of the memory subsystem. The variable length column command is provided to the memory subsystem based on a detection of a plurality of accesses directed to the same page. The memory subsystem, upon receiving a variable length column command, is configured to perform a corresponding plurality of accesses indicated by the variable length column command

公开(公告)号：US20180136845A1

公开(公告)日：2018-05-17

申请号：US15854622

申请日：2017-12-26

Applicant: Micron Technology, Inc.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/16 ,  G06F13/42 ,  G11C8/12 ,  G11C11/5642 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C2207/2209

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.