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    Method of forming a capacitor plate and a capacitor incorporating same
    41.
    发明授权
    Method of forming a capacitor plate and a capacitor incorporating same 失效
    形成电容器板的方法和结合其的电容器

    公开(公告)号：US5955758A

    公开(公告)日：1999-09-21

    申请号：US738789

    申请日：1996-10-29

    Applicant: Gurtej S. Sandhu ,  Paul Schuele ,  Wayne Kinney

    Inventor： Gurtej S. Sandhu ,  Paul Schuele ,  Wayne Kinney

    IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108

    CPC classification number: H01L27/11502 ,  H01L27/1085 ,  H01L27/11507 ,  H01L28/40 ,  H01L27/10852

    Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing an electrically conductive first layer over the node; c) providing an electrically insulative barrier second layer over the first conductive layer; d) providing a third layer over the electrically insulative barrier layer, the third layer comprising a material which is either electrically conductive and resistant to oxidation, or forms an electrically conductive material upon oxidation; e) providing an insulating inorganic metal oxide dielectric layer over the electrically conductive third layer; f) providing an electrically conductive fourth layer over the insulating inorganic metal oxide dielectric layer; and g) providing an electrically conductive interconnect to extend over the second insulative layer and electrically interconnect the first and third conductive layers. A capacitor construction having such a dielectric layer in combination with the barrier layer and electrical interconnect of a first capacitor plate is disclosed.

    Abstract translation: 形成电容器的方法包括：a）提供与电容器进行电连接的节点; b）在节点上提供导电的第一层; c）在所述第一导电层之上提供电绝缘阻挡层第二层; d）在电绝缘阻挡层上提供第三层，第三层包括导电并耐氧化的材料，或者在氧化时形成导电材料; e）在导电的第三层之上提供绝缘的无机金属氧化物介电层; f）在绝缘无机金属氧化物介电层上提供导电第四层; 以及g）提供导电互连以在所述第二绝缘层上延伸并且使所述第一和第三导电层电互连。 公开了一种电容器结构，其具有与阻挡层和第一电容器板的电互连结合的这种介电层。

    NON-VOLATILE MEMORY DEVICE ION BARRIER
    42.
    发明申请
    NON-VOLATILE MEMORY DEVICE ION BARRIER 失效
    非易失性存储器件隔离器

    公开(公告)号：US20120300535A1

    公开(公告)日：2012-11-29

    申请号：US13570871

    申请日：2012-08-09

    Applicant: Lawrence Schloss ,  Rene Meyer ,  Wayne Kinney ,  Roy Lambertson ,  Julie Casperson Brewer

    Inventor： Lawrence Schloss ,  Rene Meyer ,  Wayne Kinney ,  Roy Lambertson ,  Julie Casperson Brewer

    IPC: H01L45/00 ,  G11C11/21

    CPC classification number: G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

    Abstract: An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

    Abstract translation: 由与电绝缘层接触的介电材料制成的离子阻挡层可操作以防止在对非易失性存储单元的数据操作期间传输到电绝缘层中的移动离子通过离子阻挡层并进入相邻层。 与电绝缘层接触的导电氧化物层是可移动离子的源。 编程数据操作用于将一部分移动离子传输到电绝缘层中，并且擦除数据操作可操作以将移动离子传输回到导电氧化物层中。 当该部分位于电绝缘层中时，存储单元将数据存储为编程电导率分布，并且当大部分移动离子位于导电氧化物层中时，存储单元将数据存储为擦除的电导率分布。

    Conductive metal oxide structures in non-volatile re-writable memory devices
    43.
    发明授权
    Conductive metal oxide structures in non-volatile re-writable memory devices 有权
    非易失性可重写存储器件中的导电金属氧化物结构

    公开(公告)号：US08031509B2

    公开(公告)日：2011-10-04

    申请号：US12653836

    申请日：2009-12-18

    Applicant: Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Rene Meyer

    Inventor： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Rene Meyer

    IPC: G11C11/00

    CPC classification number: H01L45/085 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C2013/0073 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76

    Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

    Abstract translation: 公开了包括与导电金属氧化物（CMO）接触的电解绝缘体的存储元件的存储单元。 CMO包括晶体结构并且可以包含烧绿石氧化物，导电二元氧化物，多个B位钙钛矿和Ruddlesden-Popper结构。 CMO包括可以响应于施加在电解绝缘体和CMO上施加的写入电压产生的适当幅度和方向的电场，可以将其输送到电解绝缘体/从电解绝缘体传输的移动离子。 存储器单元可以包括与存储元件电串联的非欧姆器件（NOD）。 存储器单元可以位于单层存储器中的两端交叉点存储器阵列中的导电阵列线的交叉点或多个垂直堆叠的存储器层之间，该衬底层在衬底上制造，该衬底包括用于数据的有源电路 对数组层进行操作。

    Conductive metal oxide structures in non-volatile re-writable memory devices
    44.
    发明申请
    Conductive metal oxide structures in non-volatile re-writable memory devices 有权
    非易失性可重写存储器件中的导电金属氧化物结构

    公开(公告)号：US20100157658A1

    公开(公告)日：2010-06-24

    申请号：US12653836

    申请日：2009-12-18

    Applicant: Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Rene Meyer

    Inventor： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Rene Meyer

    IPC: G11C11/56

    CPC classification number: H01L45/085 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C2013/0073 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76

    Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

    Abstract translation: 公开了包括与导电金属氧化物（CMO）接触的电解绝缘体的存储元件的存储单元。 CMO包括晶体结构并且可以包含烧绿石氧化物，导电二元氧化物，多个B位钙钛矿和Ruddlesden-Popper结构。 CMO包括可以响应于施加在电解绝缘体和CMO上施加的写入电压产生的适当幅度和方向的电场，可以将其输送到电解绝缘体/从电解绝缘体传输的移动离子。 存储器单元可以包括与存储元件电串联的非欧姆器件（NOD）。 存储器单元可以位于单层存储器中的两端交叉点存储器阵列中的导电阵列线的交叉点或多个垂直堆叠的存储器层之间，该衬底层在衬底上制造，该衬底包括用于数据的有源电路 对数组层进行操作。

    Memory using variable tunnel barrier widths
    46.
    发明申请
    Memory using variable tunnel barrier widths 失效
    使用可变隧道势垒宽度的内存

    公开(公告)号：US20090231906A1

    公开(公告)日：2009-09-17

    申请号：US12454698

    申请日：2009-05-21

    Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Edmond Ward

    Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Edmond Ward

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/02 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/54 ,  G11C2213/71 ,  H01L27/115 ,  H01L27/2436 ,  H01L27/2481 ,  H01L29/8616 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

    Abstract: A memory using a tunnel barrier that has a variable effective width is disclosed. A memory element includes a tunneling barrier and a conductive material. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is either formed or destroyed. It can be formed by either the depletion or excess ions around the tunneling barrier, or by the mobile ions combining with complementary ions. It may be destroyed by either reversing the forming process or by reducing the tunneling barrier and injecting ions into the conductive material. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity multiple states can be created in the memory cell.

    Abstract translation: 公开了一种使用具有可变有效宽度的隧道势垒的存储器。 存储元件包括隧道势垒和导电材料。 导电材料通常具有响应于存储元件两端的电压而移动或者远离隧道势垒的移动离子。 形成或破坏低导电性区域。 它可以通过隧道势垒周围的耗尽或过量离子，或通过与互补离子组合的移动离子来形成。 可能通过反转成形过程或减少隧道势垒并将离子注入导电材料来破坏。 低导电率区域增加了隧道势垒的有效宽度，使得电子隧道更大的距离，这降低了存储元件的导电性。 通过改变电导率，可以在存储器单元中产生多个状态。

    Threshold device for a memory array
    48.
    发明申请
    Threshold device for a memory array 失效
    内存阵列的阈值设备

    公开(公告)号：US20090027976A1

    公开(公告)日：2009-01-29

    申请号：US11881473

    申请日：2007-07-26

    Applicant: Julie Casperson Brewer ,  Darrell Rinerson ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Lawrence Schloss

    Inventor： Julie Casperson Brewer ,  Darrell Rinerson ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Lawrence Schloss

    IPC: G11C7/00

    CPC classification number: G11C7/02 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/147

    Abstract: A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.

    Abstract translation: 公开了一种阈值装置，其包括彼此接触并且由多种不同介电材料制成的多个相邻隧道势垒层。 具有第一和第二端子的存储器插头包括与第一和第二端子串联的阈值装置和存储数据作为多个导电率曲线的存储元件。 阈值装置可操作以在数据操作期间根据施加的电压施加限定通过存储元件的电流的特征I-V曲线。 阈值装置基本上减少或消除了通过半选择或未选择的存储器插头的电流，并且允许足够大的电流流过被选择用于读取和写入操作的存储器插头。 阈值器件减少或消除半选择的存储器插头中的数据干扰，并在读取操作期间增加S / N比。

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