公开(公告)号：US10134596B1

公开(公告)日：2018-11-20

申请号：US15820168

申请日：2017-11-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Yoshikazu Kondo ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/205 ,  H01L21/28 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L29/778 ,  H01L21/02

Abstract: In some embodiments, an apparatus includes a first layer with a first surface and a second surface opposite to the first surface. The apparatus also includes a second layer having a third surface interfacing the second surface and a fourth surface opposite the third surface. The apparatus further includes a third layer having a fifth surface interfacing the fourth surface and a sixth surface opposite the fifth surface. The apparatus also includes a fourth layer having a seventh surface interfacing the sixth surface to form a heterojunction, which generates a two-dimensional electron gas channel formed in the fourth layer. Further, the apparatus includes a recess that extends from the first surface to the fifth surface.

公开(公告)号：US20180308773A1

公开(公告)日：2018-10-25

申请号：US16010654

申请日：2018-06-18

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Sameer Pendharkar

IPC: H01L21/66 ,  G01R31/28 ,  H01L27/088 ,  H01L29/06 ,  H01L23/544 ,  H01L29/20 ,  H01L29/417 ,  G01R31/12 ,  H01L29/40

CPC classification number: H01L22/34 ,  G01R31/12 ,  G01R31/2621 ,  G01R31/2642 ,  H01L23/544 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/41725

Abstract: A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer between 0 and N inclusive. A test structure TSX of the first set of test structures includes a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate and a respective drain contact abutting the GaN substrate. The test structure TSX also includes a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X respective field plates including field plates that are nearest to the GaN substrate.

公开(公告)号：US10103258B2

公开(公告)日：2018-10-16

申请号：US15394636

申请日：2016-12-29

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66 ,  H01L23/52 ,  H01L21/22 ,  H01L21/28 ,  H01L29/423 ,  H01L23/528

Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

公开(公告)号：US09947784B2

公开(公告)日：2018-04-17

申请号：US15364817

申请日：2016-11-30

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland Hower ,  Sameer Pendharkar ,  Marie Denison

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L21/266 ,  H01L21/324 ,  H01L21/225

CPC classification number: H01L29/7816 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.

公开(公告)号：US20180053765A1

公开(公告)日：2018-02-22

申请号：US15681466

申请日：2017-08-21

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Binghua Hu ,  Alexei Sadovnikov ,  Guru Mathur

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06

Abstract: A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.

公开(公告)号：US09899484B1

公开(公告)日：2018-02-20

申请号：US15395015

申请日：2016-12-30

Applicant: Texas Instruments Incorporated

Inventor： Hiroyuki Tomomatsu ,  Hiroshi Yamasaki ,  Sameer Pendharkar

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/41 ,  H01L29/45 ,  H01L29/49 ,  H01L27/06 ,  H01L29/417 ,  H01L29/778

CPC classification number: H01L29/404 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/452 ,  H01L29/4966 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787

Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.

公开(公告)号：US09865729B1

公开(公告)日：2018-01-09

申请号：US15385709

申请日：2016-12-20

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Ming-yeh Chuang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/408 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/66689

Abstract: A power transistor is provided with at least one transistor finger that lies within a semiconductor material. The gate oxide is segmented into a set of segments with thick field oxide between each segment in order to reduce gate capacitance and thereby improve a resistance times gate charge figure of merit.

公开(公告)号：US09865722B2

公开(公告)日：2018-01-09

申请号：US15380280

申请日：2016-12-15

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H01L29/72 ,  H01L29/778 ,  H01L29/20 ,  H01L27/06 ,  H01L27/02 ,  H01L29/205 ,  H01L49/02

CPC classification number: H01L29/7787 ,  H01L21/8232 ,  H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7833

Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

公开(公告)号：US09793375B2

公开(公告)日：2017-10-17

申请号：US15013334

申请日：2016-02-02

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland Hower ,  Sameer Pendharkar ,  Marie Denison

IPC: H01L29/66 ,  H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L21/266 ,  H01L27/088 ,  H01L21/225

CPC classification number: H01L29/66681 ,  H01L21/2253 ,  H01L21/266 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

公开(公告)号：US09412668B2

公开(公告)日：2016-08-09

申请号：US14712148

申请日：2015-05-14

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.