Invention Application
- Patent Title: DUAL DEEP TRENCHES FOR HIGH VOLTAGE ISOLATION
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Application No.: US15681466Application Date: 2017-08-21
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Publication No.: US20180053765A1Publication Date: 2018-02-22
- Inventor: Sameer Pendharkar , Binghua Hu , Alexei Sadovnikov , Guru Mathur
- Applicant: Texas Instruments Incorporated
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238 ; H01L29/06

Abstract:
A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.
Public/Granted literature
- US10580775B2 Dual deep trenches for high voltage isolation Public/Granted day:2020-03-03
Information query
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