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公开(公告)号：US20160118583A1
公开(公告)日：2016-04-28
申请号：US14985102
申请日：2015-12-30
Inventor： Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L45/04 , H01L45/122 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1666 , H01L45/1675
Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
Abstract translation: 一种存储单元和方法，包括通过第一电介质层中的第一开口形成的第一电极，形成在第一电极上的电阻层，形成在电阻层上的间隔层，形成在电阻层上的第二电极，以及第二电极 形成在第二电极上的电介质层，第二电介质层包括第二开口。 形成在包括第一金属层的基板上的第一电介质层。 第一电极和电阻层共同地包括第一距离超过第一开口延伸的第一唇缘区域。 第二电极和第二电介质层共同包括延伸第二距离超过第一开口的第二唇缘区域。 间隔层从第二距离延伸到第一距离。 使用延伸穿过第二开口的通孔将第二电极耦合到第二金属层。
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公开(公告)号：US20140131651A1
公开(公告)日：2014-05-15
申请号：US13674193
申请日：2012-11-12
Inventor： Kuo-Chi Tu , Wen-Ting Chu , Yu-Wen Liao , Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L45/04 , H01L45/122 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond a region defined by the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the region defined by the first opening. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
Abstract translation: 一种存储单元和方法，包括通过第一电介质层中的第一开口保形地形成的第一电极，保形地形成在第一电极上的电阻层，保形地形成在电阻层上的第二电极和保形地形成在第一电介质层上的第二电介质层 第二电极，第二介电层包括第二开口。 第一介电层形成在包括第一金属层的基板上。 第一电极和电阻层共同地包括第一距离超过由第一开口限定的区域延伸的第一唇缘区域。 第二电极和第二电介质层共同包括延伸第二距离超过由第一开口限定的区域的第二唇缘区域。 使用延伸穿过第二开口的通孔将第二电极耦合到第二金属层。
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公开(公告)号：US20250048647A1
公开(公告)日：2025-02-06
申请号：US18921069
申请日：2024-10-21
Inventor： Chih-Hsiang Chang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Tzu-Yu Chen , Fu-Chen Chang
Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.
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公开(公告)号：US12218005B2
公开(公告)日：2025-02-04
申请号：US18422726
申请日：2024-01-25
Inventor： Hsia-Wei Chen , Fu-Ting Sung , Yu-Wen Liao , Wen-Ting Chu , Fa-Shen Jiang , Tzu-Hsuan Yeh
IPC: H01L21/768 , H01L23/528 , H01L23/532
Abstract: An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.
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公开(公告)号：US11980041B2
公开(公告)日：2024-05-07
申请号：US17829572
申请日：2022-06-01
Inventor： Hsia-Wei Chen , Wen-Ting Chu , Yu-Wen Liao
Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.
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Patent Agency Ranking
公开(公告)号：US11869564B2
公开(公告)日：2024-01-09
申请号：US17866946
申请日：2022-07-18
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Wen-Ting Chu , Yong-Shiuan Tsair
CPC classification number: G11C11/2259 , G11C11/223 , G11C11/2255 , G11C11/2257 , H01L29/516 , H10B51/30 , H10B51/40
Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is disposed over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random-access memory (FeRAM) device is disposed over the substrate between the select gate and the first source/drain region. A first sidewall spacer, including one or more dielectric materials, is arranged laterally between the select gate and the FeRAM device. An inter-level dielectric (ILD) structure laterally surrounds the FeRAM device and the select gate and vertically overlies a top surface of the first sidewall spacer.
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公开(公告)号：US11856788B2
公开(公告)日：2023-12-26
申请号：US17192227
申请日：2021-03-04
Inventor： Tzu-Yu Chen , Sheng-Hung Shih , Fu-Chen Chang , Kuo-Chi Tu , Wen-Ting Chu , Alexander Kalnitsky
Abstract: A method for fabricating a semiconductor device is provided. The method includes depositing a bottom electrode layer over a substrate; depositing a ferroelectric layer over the bottom electrode layer; depositing a first top electrode layer over the ferroelectric layer, wherein the first top electrode layer comprises a first metal; depositing a second top electrode layer over the first top electrode layer, wherein the second top electrode layer comprises a second metal, and a standard reduction potential of the first metal is greater than a standard reduction potential of the second metal; and removing portions of the second top electrode layer, the first top electrode layer, the ferroelectric layer, and the bottom electrode layer to form a memory stack, the memory stack comprising remaining portions of the second top electrode layer, the first top electrode layer, the ferroelectric layer, and the bottom electrode layer.
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公开(公告)号：US11832529B2
公开(公告)日：2023-11-28
申请号：US17724920
申请日：2022-04-20
Inventor： Harry-Hak-Lay Chuang , Hung Cho Wang , Tong-Chern Ong , Wen-Ting Chu , Yu-Wen Liao , Kuei-Hung Shen , Kuo-Yuan Tu , Sheng-Huang Huang
CPC classification number: H10N50/80 , H10N50/01 , H10N50/10 , H10N50/85 , H10N70/011 , H10N70/021 , H10N70/063 , H10N70/20 , H10N70/826 , H10N70/8833
Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.
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公开(公告)号：US20230371263A1
公开(公告)日：2023-11-16
申请号：US18357240
申请日：2023-07-24
Inventor： Chih-Hsiang Chang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Tzu-Yu Chen , Fu-Chen Chang
CPC classification number: H10B51/00 , G11C11/223 , H01L29/78391 , H01L29/516 , H01L29/6684 , H01L29/40111
Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.
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公开(公告)号：US11737290B2
公开(公告)日：2023-08-22
申请号：US17542638
申请日：2021-12-06
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Wen-Ting Chu , Yu-Wen Liao
IPC: H10B63/00 , G11C13/00 , H10N70/20 , H10N70/00 , H01L23/522 , H01L23/528 , H01L27/10
CPC classification number: H10B63/82 , G11C13/0011 , G11C13/0069 , H10B63/30 , H10B63/80 , H10N70/063 , H10N70/20 , H10N70/24 , H10N70/826 , H10N70/841 , H10N70/8833 , H10N70/8836 , G11C13/004 , G11C13/0023 , G11C2213/79 , H01L23/5226 , H01L23/5283 , H01L27/101 , H10B63/84 , H10N70/011 , H10N70/023 , H10N70/821 , H10N70/8845
Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.
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