公开(公告)号：US11894267B2

公开(公告)日：2024-02-06

申请号：US17141852

申请日：2021-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsia-Wei Chen ,  Fu-Ting Sung ,  Yu-Wen Liao ,  Wen-Ting Chu ,  Fa-Shen Jiang ,  Tzu-Hsuan Yeh

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76832 ,  H01L23/528 ,  H01L23/53209

Abstract: A method for fabricating an integrated circuit device is provided. The method includes forming an interconnect layer over a substrate, wherein the interconnect layer has a first interlayer dielectric layer, a first conductive feature in a first portion of the first interlayer dielectric layer, and a second conductive feature in a second portion of the first interlayer dielectric layer; depositing a dielectric layer over the interconnect layer; removing a first portion of the dielectric layer over the first conductive feature and the first portion of the first interlayer dielectric layer, and remaining a second portion of the dielectric layer over the second conductive feature and the second portion of the first interlayer dielectric layer; and forming a memory structure over the first conductive feature.

公开(公告)号：US20230369260A1

公开(公告)日：2023-11-16

申请号：US18357350

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Hsuan Yeh ,  Chern-Yow Hsu

IPC: H01L23/00 ,  H01L21/308

CPC classification number: H01L24/03 ,  H01L21/308 ,  H01L24/05 ,  H01L2224/03831

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of interconnects disposed within a dielectric structure over a substrate. A conductor is disposed over at least one of the plurality of interconnects. A protective layer is disposed on the conductor and a mask layer is disposed on the protective layer. One or more passivation layers are disposed on the mask layer. The protective layer, the mask layer, and the one or more passivation layers respectively have one or more sidewalls directly over the conductor.

公开(公告)号：US12165996B2

公开(公告)日：2024-12-10

申请号：US18357350

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Hsuan Yeh ,  Chern-Yow Hsu

IPC: H01L23/00 ,  H01L21/308

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of interconnects disposed within a dielectric structure over a substrate. A conductor is disposed over at least one of the plurality of interconnects. A protective layer is disposed on the conductor and a mask layer is disposed on the protective layer. One or more passivation layers are disposed on the mask layer. The protective layer, the mask layer, and the one or more passivation layers respectively have one or more sidewalls directly over the conductor.

公开(公告)号：US20240379594A1

公开(公告)日：2024-11-14

申请号：US18783824

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Hsuan Yeh ,  Chern-Yow Hsu

IPC: H01L23/00 ,  H01L21/308

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive feature disposed over a dielectric structure on a substrate. A first layer is arranged on peripheral regions of the conductive feature. A second layer has a bottommost surface arranged on the first layer. The second layer includes a material that etches at a higher rate than the first layer when exposed to a first etchant and that etches at a lower rate than the first layer when exposed to a second etchant. An additional conductive feature extends through the first layer and the second layer to contact the conductive feature.

公开(公告)号：US12218005B2

公开(公告)日：2025-02-04

申请号：US18422726

申请日：2024-01-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsia-Wei Chen ,  Fu-Ting Sung ,  Yu-Wen Liao ,  Wen-Ting Chu ,  Fa-Shen Jiang ,  Tzu-Hsuan Yeh

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.

公开(公告)号：US11824022B2

公开(公告)日：2023-11-21

申请号：US17590411

申请日：2022-02-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Hsuan Yeh ,  Chern-Yow Hsu

IPC: H01L23/00 ,  H01L21/308

CPC classification number: H01L24/03 ,  H01L21/308 ,  H01L24/05 ,  H01L2224/03831

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bond pad disposed over a substrate and a passivation structure disposed over the substrate and the bond pad. The passivation structure has one or more sidewalls directly over the bond pad. A protective layer is disposed directly between the passivation structure and the bond pad. The passivation structure extends from directly over the protective layer to laterally past a sidewall of the protective layer that faces a central region of the bond pad.

公开(公告)号：US20220157751A1

公开(公告)日：2022-05-19

申请号：US17590411

申请日：2022-02-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Hsuan Yeh ,  Chern-Yow Hsu

IPC: H01L23/00 ,  H01L21/308

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bond pad disposed over a substrate and a passivation structure disposed over the substrate and the bond pad. The passivation structure has one or more sidewalls directly over the bond pad. A protective layer is disposed directly between the passivation structure and the bond pad. The passivation structure extends from directly over the protective layer to laterally past a sidewall of the protective layer that faces a central region of the bond pad.