公开(公告)号：US11500960B2

公开(公告)日：2022-11-15

申请号：US16666699

申请日：2019-10-29

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Ye Lu ,  Yandong Gao ,  Xiaochun Zhu ,  Xia Li

IPC: G11C11/419 ,  G06F17/16 ,  G11C11/412 ,  G06N3/063

Abstract: Certain aspects provide a circuit for in-memory computation. The circuit generally includes an in-memory computation array having a plurality of computation circuits, each of the computation circuits being configured to perform a dot product computation. In certain aspects, each of the computation circuits includes a memory cell, a capacitive element, a precharge transistor coupled between an output of the memory cell and the capacitive element, and a read transistor coupled between a read bit line (RBL) and the capacitive element.

公开(公告)号：US20220172770A1

公开(公告)日：2022-06-02

申请号：US17404378

申请日：2021-08-17

Applicant: QUALCOMM Incorporated

Inventor： Xiaonan Chen ,  Zhongze Wang

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/408 ,  G11C5/06 ,  H03K19/017 ,  H03K19/20

Abstract: Compute-in-memory (CIM) bit cell array circuits include CIM bit cell circuits for multiply-accumulate operations. The CIM bit cell circuits include a memory bit cell circuit for storing a weight data in true and complement form. The CIM bit cell circuits include a true pass-gate circuit and a complement pass-gate circuit for generating a binary product of the weight data and an activation input on a product node. An RWL circuit couples the product node to a ground voltage for initialization. The CIM bit cell circuits also include a plurality of consecutive gates each coupled to at least one of the memory bit cell circuit, the true pass-gate circuit, the complement pass-gate circuit, and the RWL circuit. Each of the CIM bit cell circuits in the CIM bit cell array circuit is disposed in an orientation of a CIM bit cell circuit layout including the RWL circuit.

公开(公告)号：US09876123B2

公开(公告)日：2018-01-23

申请号：US14495507

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Bin Yang ,  Jun Yuan ,  Xiaonan Chen ,  Zhongze Wang

IPC: G11C16/10 ,  H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  G11C17/18 ,  H01L27/112 ,  G11C16/26 ,  G11C16/04

CPC classification number: H01L29/792 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C17/18 ,  H01L27/11206 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.

公开(公告)号：US09876017B2

公开(公告)日：2018-01-23

申请号：US14559258

申请日：2014-12-03

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/11 ,  H01L23/528 ,  H01L27/02 ,  G11C5/06 ,  G11C8/14 ,  G11C11/418 ,  G11C11/412 ,  G11C8/16 ,  H01L21/768

CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have wider widths, which decrease wordline resistance, decrease access time, and increase performance of SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks inside and outside of a boundary edge of the SRAM bit cell. Landing pads corresponding to the write wordline are placed on corresponding tracks within the boundary edge of the SRAM bit cell.

公开(公告)号：US09842802B2

公开(公告)日：2017-12-12

申请号：US14227415

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  John Jianhong Zhu ,  Xia Li

IPC: H01L21/82 ,  H01L27/112 ,  H01L21/8239 ,  H01L23/525 ,  G11C17/16 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5252 ,  G11C17/16 ,  H01L23/5228 ,  H01L27/11206 ,  H01L27/11286 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first conductor plate, a dielectric layer, and a second conductor plate, where the dielectric layer is interposed between the first and second conductor plates. The antifuse transitions from an open circuit state to a closed circuit state if a programming voltage Vpp greater than or equal to a dielectric breakdown voltage VBD of the antifuse is applied to the first conductor plate and the second conductor plate. The first conductor plate has a total edge length that is greater than two times the sum of its maximum width and maximum length dimensions. The first conductor plate's top surface area may also be less than the product of its maximum length and maximum width.

公开(公告)号：US09691868B2

公开(公告)日：2017-06-27

申请号：US14283168

申请日：2014-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: H01L29/423 ,  G03F7/20 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L29/4238 ,  G03F7/70466 ,  H01L21/28123 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0886

Abstract: Methods for fabricating devices on a die, and devices on a die. A method may include patterning a first region to create a first gate having a first gate length and a first contacted polysilicon pitch (CPP) with a first process. The first CPP is smaller than a single pattern lithographic limit. The method also includes patterning the first region to create a second gate having a second gate length or a second CPP with a second process. The second CPP is smaller than the single pattern lithographic limit. The second gate length is different than the first gate length.

公开(公告)号：US09536596B2

公开(公告)日：2017-01-03

申请号：US14468976

申请日：2014-08-26

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C11/40 ,  G11C11/419 ,  G11C7/18 ,  G11C8/16 ,  G11C11/412 ,  G11C29/00 ,  H01L27/02 ,  H01L27/11 ,  H01L21/3213 ,  H01L21/768

CPC classification number: G11C11/419 ,  G11C7/18 ,  G11C8/16 ,  G11C11/40 ,  G11C11/412 ,  G11C29/816 ,  H01L21/32133 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/1104

Abstract: An apparatus includes a first read port, a second read port, a write port, and at least one storage latch. A width of a bit cell that includes the first read port, the second read port, and the write port is greater than twice a contacted poly pitch (CPP) associated with the bit cell. For example, a bit cell may be a 3-port static random access memory (SRAM) bit cell that is compatible with self-aligned double patterning (SADP) processes and that can be manufactured using semiconductor manufacturing processes of less than 14 nanometers (nm).

Abstract translation: 一种装置包括第一读取端口，第二读取端口，写入端口和至少一个存储锁存器。 包括第一读取端口，第二读取端口和写入端口的位单元的宽度大于与位单元相关联的接触多边距（CPP）的两倍。 例如，位单元可以是与自对准双图案（SADP）工艺兼容的3端口静态随机存取存储器（SRAM）位单元，并且可以使用小于14纳米（nm）的半导体制造工艺来制造 ）。

公开(公告)号：US09496048B2

公开(公告)日：2016-11-15

申请号：US14656699

申请日：2015-03-12

Applicant: QUALCOMM Incorporated

Inventor： Xiaonan Chen ,  Zhongze Wang ,  Xia Li

IPC: G11C17/08

CPC classification number: G11C17/08 ,  G11C7/04 ,  G11C17/12 ,  G11C17/123

Abstract: An OTP memory array includes a plurality of differential P-channel metal oxide semiconductor (PMOS) OTP memory cells programmable and readable in predetermined states of program and read operations, and is capable of providing sufficient margins against global process variations and temperature variations while being compatible with standard logic fin-shaped field effect transistor (FinFET) processes to obviate the need for additional masks and costs associated with additional masks.

Abstract translation: OTP存储器阵列包括在预定的程序和读取操作状态下可编程和可读的多个差分P沟道金属氧化物半导体（PMOS）OTP存储器单元，并且能够在兼容的同时为全局工艺变化和温度变化提供足够的余量 具有标准逻辑鳍状场效应晶体管（FinFET）处理，以避免需要额外的掩模和与附加掩模相关联的成本。

公开(公告)号：US09431097B2

公开(公告)日：2016-08-30

申请号：US14579891

申请日：2014-12-22

Applicant: QUALCOMM Incorporated

Inventor： Xiaonan Chen ,  Zhongze Wang ,  Xia Li

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C11/4125 ,  G11C14/0054

Abstract: A method of operation of a static random access memory (SRAM) storage element includes programming a value to the SRAM storage element prior to a power-down event. The method further includes, in response to a power-on event at the SRAM storage element after the power-down event, increasing a supply voltage of the SRAM storage element and sensing a state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event. In a particular example, an apparatus includes the SRAM storage element and control circuitry coupled to the SRAM storage element. The control circuitry may be configured to program the value to the SRAM storage element, to increase the supply voltage, and to sense the state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event.

Abstract translation: 静态随机存取存储器（SRAM）存储元件的操作方法包括在掉电事件之前将值编程到SRAM存储元件。 该方法还包括响应于在掉电事件之后的SRAM存储元件处的电源接通事件，增加SRAM存储元件的电源电压并感测SRAM存储元件的状态，以确定被编程到 SRAM存储元件在掉电事件之前。 在特定示例中，装置包括耦合到SRAM存储元件的SRAM存储元件和控制电路。 控制电路可以被配置为将值编程到SRAM存储元件，以增加电源电压，并且感测SRAM存储元件的状态以确定在掉电事件之前被编程到SRAM存储元件的值。

公开(公告)号：US20160180925A1

公开(公告)日：2016-06-23

申请号：US14579891

申请日：2014-12-22

Applicant: QUALCOMM Incorporated

Inventor： Xiaonan Chen ,  Zhongze Wang ,  Xia Li

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C11/4125 ,  G11C14/0054

Abstract: A method of operation of a static random access memory (SRAM) storage element includes programming a value to the SRAM storage element prior to a power-down event. The method further includes, in response to a power-on event at the SRAM storage element after the power-down event, increasing a supply voltage of the SRAM storage element and sensing a state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event. In a particular example, an apparatus includes the SRAM storage element and control circuitry coupled to the SRAM storage element. The control circuitry may be configured to program the value to the SRAM storage element, to increase the supply voltage, and to sense the state of the SRAM storage element to determine the value programmed to the SRAM storage element prior to the power-down event.

Abstract translation: 静态随机存取存储器（SRAM）存储元件的操作方法包括在掉电事件之前将值编程到SRAM存储元件。 该方法还包括响应于在掉电事件之后的SRAM存储元件处的电源接通事件，增加SRAM存储元件的电源电压并感测SRAM存储元件的状态，以确定被编程到 SRAM存储元件在掉电事件之前。 在特定示例中，装置包括耦合到SRAM存储元件的SRAM存储元件和控制电路。 控制电路可以被配置为将值编程到SRAM存储元件，以增加电源电压，并且感测SRAM存储元件的状态以确定在掉电事件之前被编程到SRAM存储元件的值。