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62 条记录 (耗时 0.012 秒)

    Semiconductor device and method of manufacturing the same
    42.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US06724045B1

    公开(公告)日：2004-04-20

    申请号：US09713251

    申请日：2000-11-16

    申请人： Yukihiro Ushiku

    发明人： Yukihiro Ushiku

    IPC分类号： H01L310392

    CPC分类号： H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/78612 ,  H01L29/78696 ,  H01L29/7881

    摘要： In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions are formed at the equal height on the semiconductor substrate and then a plurality of SOI-Si layers appropriately different in thickness are formed. In this manner, it is possible to obtain element isolation regions having substantially the same height from the semiconductor substrate and desired element regions having SOI-Si layers different in height. The thickness of a single crystalline silicon film (SOI-Si layer) may be appropriately changed by another method which includes depositing an amorphous silicon film and applying a heat processing to form an epi layer, and removing an unnecessary portion.

    Method of manufacturing insulated-gate type field effect transistor
    44.
    发明授权
    Method of manufacturing insulated-gate type field effect transistor 失效
    绝缘栅型场效应晶体管的制造方法

    公开(公告)号：US5185279A

    公开(公告)日：1993-02-09

    申请号：US673669

    申请日：1991-03-22

    申请人： Yukihiro Ushiku

    发明人： Yukihiro Ushiku

    IPC分类号： H01L21/266 ,  H01L21/336 ,  H01L21/8238

    CPC分类号： H01L29/66575 ,  H01L21/266 ,  H01L21/823807 ,  H01L29/6656 ,  Y10S148/082

    摘要： A method of manufacturing an insulated-gate type field effect transistor includes the steps of forming an insulating film, on a semiconductor substrate, forming a first polycrystalline silicon layer on the insulating film, forming a second polycrystalline silicon layer on the frist polycrystalline silicon layer, patterning the first and second polycrystalline silicon layers to form a gate electrode and a masking layer, doping an impurity of a first conductivity type in the semiconductor substrate using the gate electrode and the masking layer as masks, thereby forming a source region and a drain region, starting etching the masking layer, detecting a natural oxide film on the gate electrode, stopping the etching, and ion-implanting an impurity of a second conductivity type in a region of the semiconductor substrate under the gate electrode through the gate electrode, thereby forming a channel-doped region. In this method, after the source and drain regions are formed, the impurity of the second conductivity type is ion-implanted in the substrate through the thin gate electrode to form the channel-doped region.

    摘要翻译： 一种制造绝缘栅型场效应晶体管的方法包括以下步骤：在半导体衬底上形成绝缘膜，在绝缘膜上形成第一多晶硅层，在第一多晶硅层上形成第二多晶硅层; 构图第一和第二多晶硅层以形成栅电极和掩模层，使用栅电极和掩模层作为掩模在半导体衬底中掺杂第一导电类型的杂质，由此形成源区和漏区 ，开始蚀刻掩模层，检测栅电极上的自然氧化膜，停止蚀刻，并通过栅电极在栅电极下的半导体衬底的区域中离子注入第二导电类型的杂质，从而形成 沟道掺杂区域。 在该方法中，在形成源极和漏极区之后，通过薄栅电极将第二导电类型的杂质离子注入衬底中以形成沟道掺杂区。

    Clock driver distribution system in a semiconductor integrated circuit device
    45.
    发明授权
    Clock driver distribution system in a semiconductor integrated circuit device 失效
    半导体集成电路器件中的时钟驱动器分配系统

    公开(公告)号：US4661721A

    公开(公告)日：1987-04-28

    申请号：US767847

    申请日：1985-08-21

    申请人： Yukihiro Ushiku

    发明人： Yukihiro Ushiku

    IPC分类号： H03K5/00 ,  G06F1/10 ,  H03K5/15 ,  H03K19/01

    CPC分类号： G06F1/10

    摘要： A semiconductor integrated circuit device wherein a plurality of clock signal lines provided with a clock signal are drawn out independently from the respective output terminals of a plurality of divided clock drivers, the clock signal lines being connected together by a common connecting line.

    摘要翻译： 一种半导体集成电路器件，其中设置有时钟信号的多个时钟信号线与多个分频时钟驱动器的各个输出端独立地被抽出，时钟信号线通过公共连接线连接在一起。

    Multilayer interconnection structure for semiconductor device
    46.
    发明授权
    Multilayer interconnection structure for semiconductor device 失效
    半导体器件的多层互连结构

    公开(公告)号：US4587549A

    公开(公告)日：1986-05-06

    申请号：US482783

    申请日：1983-04-07

    申请人： Yukihiro Ushiku

    发明人： Yukihiro Ushiku

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/283 ,  H01L21/94 ,  H01L23/18

    CPC分类号： H01L23/5226 ,  H01L2924/0002

    摘要： A multilayer interconnection structure for a semiconductor device has interconnection layers superposed on each other on the surface of a semiconductor substrate with an insulating layer interposed therebetween. Connection between the desired interconnection layers or between the desired interconnection layer and semiconductor substrate is effected by means of a contact hole formed in the respective insulating layers. Two upper and lower interconnection layers intersect each other above the contact holes, and the contact hole does not overlap part of the traverse region of the upper interconnection layer in the intersecting section.

    摘要翻译： 用于半导体器件的多层互连结构具有在半导体衬底的表面上彼此重叠的互连层，其间插入有绝缘层。 期望的互连层之间或期望的互连层和半导体衬底之间的连接通过形成在各个绝缘层中的接触孔来实现。 两个上互连层和下互连层在接触孔之上彼此相交，并且接触孔不与交叉部分中的上互连层的横越区域的部分重叠。

    Process control system, process control method, and method of manufacturing electronic apparatus
    47.
    发明授权
    Process control system, process control method, and method of manufacturing electronic apparatus 有权
    过程控制系统，过程控制方法和制造电子设备的方法

    公开(公告)号：US07831330B2

    公开(公告)日：2010-11-09

    申请号：US12458421

    申请日：2009-07-10

    申请人： Junji Sugamoto ,  Yukihiro Ushiku ,  Kazutaka Akiyama ,  Shoichi Harakawa

    发明人： Junji Sugamoto ,  Yukihiro Ushiku ,  Kazutaka Akiyama ,  Shoichi Harakawa

    IPC分类号： G06F19/00

    CPC分类号： G05B19/41875 ,  G05B2219/31477 ,  G05B2219/32057 ,  G05B2219/32097 ,  G05B2219/45031 ,  Y02P90/12 ,  Y02P90/20 ,  Y02P90/22

    摘要： A process control system includes a client computer which prepares a correlation between a reference monitored value of apparatus information and a feature quantity, a manufacturing execution system which prepares a processing recipe describing, as a first setting value in an actual manufacturing process, a value of the control parameter, an apparatus information collection section which collects an objective monitored value of the apparatus information in operation of the actual manufacturing process with the first setting value, a feature quantity calculation section which calculates a value of a feature quantity corresponding to the objective monitored value based on the correlation, a parameter calculation section which calculates a second setting value in the actual manufacturing process on the basis of the value of the feature quantity, and an apparatus control unit which changes the processing recipe with the second setting value being as a setting value of the second step.

    摘要翻译： 过程控制系统包括：准备设备信息的参考监视值和特征量之间的相关性的客户端计算机;准备描述作为实际制造过程中的第一设定值的处理配方的制造执行系统， 所述控制参数，设备信息收集部分，其在具有所述第一设定值的实际制造过程的操作中收集所述设备信息的客观监视值;特征量计算部，其计算与所监视的目标对应的特征量的值 基于相关性的值，参数计算部，其基于特征量的值计算实际制造过程中的第二设定值;以及装置控制单元，其将处理配方改变为第二设定值为 设定第二步的值。

    System and method for monitoring manufacturing apparatuses
    50.
    发明授权
    System and method for monitoring manufacturing apparatuses 失效
    用于监控制造装置的系统和方法

    公开(公告)号：US07221991B2

    公开(公告)日：2007-05-22

    申请号：US11068778

    申请日：2005-03-02

    申请人： Hiroshi Matsushita ,  Tomonobu Noda ,  Kenichi Kadota ,  Junji Sugamoto ,  Yukihiro Ushiku

    发明人： Hiroshi Matsushita ,  Tomonobu Noda ,  Kenichi Kadota ,  Junji Sugamoto ,  Yukihiro Ushiku

    IPC分类号： G06F19/00

    CPC分类号： H01L22/20 ,  G01R31/2894 ,  G05B23/0248 ,  G05B2219/31357 ,  Y02P90/14

    摘要： A control system for a manufacturing apparatus includes manufacturing information input unit acquiring time series data of apparatus parameters controlling manufacturing apparatuses; failure pattern classification module classifying in-plane distributions of failures of each of the wafers into failure patterns; an index calculation unit configured to statistically process the time series data by algorithms to calculate indices corresponding to the respective algorithms; an index analysis unit providing first and second frequency distributions of the indices categorized with and without the target failure pattern, to implement significance test between the first and second frequency distributions; and an abnormal parameter extraction unit extracting failure cause index of failure pattern by comparing value of the significance test with test reference value.

    摘要翻译： 一种制造装置的控制系统，包括制造信息输入单元，其获取控制制造装置的装置参数的时间序列数据; 故障模式分类模块将每个晶片的故障平面内分布分为故障模式; 索引计算单元，被配置为通过算法对所述时间序列数据进行统计处理，以计算与各个算法对应的索引; 索引分析单元，提供分类有和没有目标故障模式的索引的第一和第二频率分布，以实现第一和第二频率分布之间的显着性测试; 异常参数提取单元通过比较显着性检验值与检测参考值，提取失效原因指标的故障模式。