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    Gate structure of semiconductor memory device
    47.
    发明授权
    Gate structure of semiconductor memory device 有权
    半导体存储器件的门结构

    公开(公告)号：US07145207B2

    公开(公告)日：2006-12-05

    申请号：US11027663

    申请日：2004-12-30

    申请人： Hong-Seon Yang ,  Se-Aug Jang ,  Yong-Soo Kim ,  Kwan-Yong Lim ,  Heung-Jae Cho ,  Jae-Geun Oh

    发明人： Hong-Seon Yang ,  Se-Aug Jang ,  Yong-Soo Kim ,  Kwan-Yong Lim ,  Heung-Jae Cho ,  Jae-Geun Oh

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L27/10873 ,  H01L27/10888

    摘要： A gate structure of a semiconductor memory device capable of preventing a poly void generation by forming a hard mask and maintaining a hysteresis area within a certain value. The gate structure of the semiconductor memory device includes: a gate insulation layer formed on a semiconductor substrate; a gate electrode formed on the gate insulation layer, wherein the gate electrode is formed by stacking a polysilicon layer and a metal layer; and a hard mask formed on the gate electrode, wherein a hysteresis area between the hard mask and the gate electrode materials is a equal to or less than approximately 2×1012 ° C.-dyne/cm2.

    摘要翻译： 一种半导体存储器件的栅极结构，其能够通过形成硬掩模并将滞后区域保持在一定值内来防止多孔隙生成。 半导体存储器件的栅极结构包括：形成在半导体衬底上的栅绝缘层; 形成在所述栅绝缘层上的栅电极，其中所述栅电极通过堆叠多晶硅层和金属层而形成; 以及形成在所述栅极电极上的硬掩模，其中所述硬掩模和所述栅极电极材料之间的滞后区域等于或小于约2×10 12·达因/ cm 2， 2 。

    Method for fabricating semiconductor device with use of partial gate recessing process
    49.
    发明授权
    Method for fabricating semiconductor device with use of partial gate recessing process 失效
    使用局部栅极凹陷工艺制造半导体器件的方法

    公开(公告)号：US07074661B2

    公开(公告)日：2006-07-11

    申请号：US10879732

    申请日：2004-06-30

    申请人： Heung-Jae Cho ,  Se-Aug Jang ,  Kwan-Yong Lim

    发明人： Heung-Jae Cho ,  Se-Aug Jang ,  Kwan-Yong Lim

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/66545 ,  H01L21/28061 ,  H01L21/823437 ,  H01L29/4941 ,  H01L29/6656

    摘要： Disclosed is a method for fabricating a semiconductor device with a polymetal gate electrode formed by a partial gate recessing process. The method includes the steps of forming a gate structure including a gate dielectric layer, a polysilicon layer, a metal layer, an etch stop layer and a sacrificial layer sequentially formed on a substrate; selectively performing a re-oxidation process to the gate structure; forming a spacer on each sidewall of the gate structure; implanting ions in the substrate for forming source/drain regions; selectively removing the sacrificial layer of the gate structure to form a recess; and filling an insulating hard mask into the recess for use in a self-aligned contact etching process.

    摘要翻译： 公开了一种通过部分栅极凹陷工艺形成的具有多金属栅电极的半导体器件的制造方法。 该方法包括以下步骤：形成栅极结构，该栅极结构包括依次形成在衬底上的栅介电层，多晶硅层，金属层，蚀刻停止层和牺牲层; 选择性地对栅极结构进行再氧化处理; 在所述栅极结构的每个侧壁上形成间隔物; 在衬底中注入离子以形成源/漏区; 选择性地去除栅极结构的牺牲层以形成凹陷; 并将绝缘硬掩模填充到凹槽中以用于自对准接触蚀刻工艺。

    Non-volatile memory device with conductive sidewall spacer and method for fabricating the same
    50.
    发明申请
    Non-volatile memory device with conductive sidewall spacer and method for fabricating the same 失效
    具有导电侧壁间隔物的非易失性存储器件及其制造方法

    公开(公告)号：US20060073666A1

    公开(公告)日：2006-04-06

    申请号：US11024472

    申请日：2004-12-30

    申请人： Kwan-Yong Lim ,  Heung-Jae Cho ,  Yong-Soo Kim ,  Se-Aug Jang ,  Hyun-Chul Sohn

    发明人： Kwan-Yong Lim ,  Heung-Jae Cho ,  Yong-Soo Kim ,  Se-Aug Jang ,  Hyun-Chul Sohn

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7887 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/66825 ,  H01L29/788

    摘要： The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.

    摘要翻译： 本发明涉及具有导电侧壁间隔物的非易失性存储器件及其制造方法。 非易失性存储器件包括：衬底; 形成在所述基板上的栅极绝缘层; 形成在栅极绝缘层上的栅极结构; 形成在所述栅极结构的侧壁上的一对侧壁间隔物; 一对导电侧壁间隔物，用于捕获/去除在一对侧壁间隔物上形成的电荷; 形成在所述衬底中的一对轻掺杂漏极区，所述衬底设置在所述栅极结构的侧壁下方; 以及形成在所述基板中的一对源极/漏极区域，所述基极设置在所述一对导电侧壁间隔物的边缘部分的下方。