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    Dual polysilicon gate of a semiconductor device with a multi-plane channel
    1.
    发明授权
    Dual polysilicon gate of a semiconductor device with a multi-plane channel 失效
    具有多平面通道的半导体器件的双多晶硅栅极

    公开(公告)号：US08471338B2

    公开(公告)日：2013-06-25

    申请号：US12632736

    申请日：2009-12-07

    申请人： Kwan-Yong Lim ,  Heung-Jae Cho ,  Min-Gyu Sung

    发明人： Kwan-Yong Lim ,  Heung-Jae Cho ,  Min-Gyu Sung

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7831 ,  H01L21/2256 ,  H01L21/28035 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851

    摘要： A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.

    摘要翻译： 半导体器件的双多晶硅栅极包括具有第一区域，第二区域和第三区域的衬底，形成在衬底的第一区域中的凹陷结构的沟道区，在衬底上形成的栅极绝缘层， 并且形成在所述第一和第二区域的所述栅极绝缘层之上的第一多晶硅层，形成在所述第三区域的所述栅极绝缘层上的第二多晶硅层和掺杂有杂质的绝缘层， 在通道区域的第一多晶硅层的内部。

    Nonvolatile memory device with multiple blocking layers and method of fabricating the same
    3.
    发明授权
    Nonvolatile memory device with multiple blocking layers and method of fabricating the same 有权
    具有多个阻挡层的非易失性存储器件及其制造方法

    公开(公告)号：US08241974B2

    公开(公告)日：2012-08-14

    申请号：US13166273

    申请日：2011-06-22

    申请人： Heung-Jae Cho ,  Moon-Sig Joo ,  Yong-Soo Kim ,  Won-Joon Choi

    发明人： Heung-Jae Cho ,  Moon-Sig Joo ,  Yong-Soo Kim ,  Won-Joon Choi

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/28282 ,  H01L21/28273

    摘要： A nonvolatile memory device with a blocking layer controlling the transfer of electric charges in a charge storage layer includes the blocking layer having a first blocking layer in contact with the charge storage layer and a second blocking layer over the first blocking layer, wherein the first blocking layer has a greater energy band gap than the second blocking layer and the second blocking layer has a greater permittivity than the first blocking layer.

    摘要翻译： 具有控制电荷存储层中的电荷转移的阻挡层的非易失性存储器件包括具有与电荷存储层接触的第一阻挡层和第一阻挡层上的第二阻挡层的阻挡层，其中第一阻塞 层具有比第二阻挡层更大的能带隙，并且第二阻挡层具有比第一阻挡层更大的介电常数。

    Method of fabricating non-volatile memory device having charge trapping layer
    5.
    发明授权
    Method of fabricating non-volatile memory device having charge trapping layer 失效
    制造具有电荷捕获层的非易失性存储器件的方法

    公开(公告)号：US07981786B2

    公开(公告)日：2011-07-19

    申请号：US11966231

    申请日：2007-12-28

    申请人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Heung Jae Cho ,  Yong Top Kim

    发明人： Moon Sig Joo ,  Seung Ho Pyi ,  Ki Seon Park ,  Heung Jae Cho ,  Yong Top Kim

    IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  Y10S438/942

    摘要： A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using the mask layer pattern as an etching mask to remove an exposed portion of the control gate electrode layer, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness, forming an insulating layer for blocking charges from moving on the control gate electrode layer and the mask layer pattern, performing anisotropic etching on the insulating layer to form an insulating layer pattern on a sidewall of the control gate electrode layer and a partial upper sidewall of the blocking layer, and performing an etching process on the blocking layer exposed by the anisotropic etching, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness.

    摘要翻译： 一种制造具有电荷捕获层的非易失性存储器件的方法包括在衬底上形成隧道层，电荷俘获层，阻挡层和控制栅电极层，在控制栅电极层上形成掩模层图案 使用掩模层图案作为蚀刻掩模进行蚀刻处理以去除控制栅电极层的暴露部分，其中蚀刻工艺作为过度蚀刻进行，以将电荷捕获层除去指定厚度，形成绝缘层 用于阻止电荷在控制栅电极层和掩模层图案上移动，对绝缘层进行各向异性蚀刻，以在控制栅电极层的侧壁和阻挡层的一部分上侧壁上形成绝缘层图案，以及 对通过各向异性蚀刻暴露的阻挡层进行蚀刻处理，其中执行蚀刻处理 作为过量蚀刻以将电荷捕获层除去指定的厚度。

    DUAL POLYSILICON GATE OF A SEMICONDUCTOR DEVICE WITH A MULTI-PLANE CHANNEL
    8.
    发明申请
    DUAL POLYSILICON GATE OF A SEMICONDUCTOR DEVICE WITH A MULTI-PLANE CHANNEL 失效
    具有多平面通道的半导体器件的双聚硅栅

    公开(公告)号：US20100084714A1

    公开(公告)日：2010-04-08

    申请号：US12632736

    申请日：2009-12-07

    申请人： Kwan-Yong LIM ,  Heung-Jae CHO ,  Min-Gyu SUNG

    发明人： Kwan-Yong LIM ,  Heung-Jae CHO ,  Min-Gyu SUNG

    IPC分类号： H01L27/092

    CPC分类号： H01L29/7831 ,  H01L21/2256 ,  H01L21/28035 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851

    摘要： A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.

    摘要翻译： 半导体器件的双多晶硅栅极包括具有第一区域，第二区域和第三区域的衬底，形成在衬底的第一区域中的凹陷结构的沟道区，在衬底上形成的栅极绝缘层， 并且形成在所述第一和第二区域的所述栅极绝缘层之上的第一多晶硅层，形成在所述第三区域的所述栅极绝缘层上的第二多晶硅层和掺杂有杂质的绝缘层， 在通道区域的第一多晶硅层的内部。

    Method for fabricating semiconductor device
    9.
    发明授权
    Method for fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07687389B2

    公开(公告)日：2010-03-30

    申请号：US11448678

    申请日：2006-06-08

    申请人： Kwan-Yong Lim ,  Min-Gyu Sung ,  Heung-Jae Cho ,  Hong-Seon Yang

    发明人： Kwan-Yong Lim ,  Min-Gyu Sung ,  Heung-Jae Cho ,  Hong-Seon Yang

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/28247

    摘要： A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, forming a first gate conductive layer over the gate insulation layer, forming a barrier metal over the first gate conductive layer, sequentially forming a second gate conductive layer and a gate hard mask over the barrier metal, patterning the gate hard mask, the second gate conductive layer, the barrier metal, the first gate conductive layer, and the gate insulation layer to form a gate pattern, and performing a plasma selective gate re-oxidation process on the gate pattern.

    摘要翻译： 一种制造半导体器件的方法包括在衬底上形成栅极绝缘层，在栅极绝缘层上形成第一栅极导电层，在第一栅极导电层上形成阻挡金属，依次形成第二栅极导电层和栅极 图案化栅极硬掩模，第二栅极导电层，势垒金属，第一栅极导电层和栅极绝缘层以形成栅极图案，并且执行等离子体选择性栅极再氧化工艺 在门模式上。

    Semiconductor device and method of fabricating the same
    10.
    发明申请
    Semiconductor device and method of fabricating the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20090325369A1

    公开(公告)日：2009-12-31

    申请号：US12318469

    申请日：2008-12-30

    申请人： Yong-Soo Kim ,  Moon-Sig Joo ,  Heung-Jae Cho ,  Won-Joon Choi

    发明人： Yong-Soo Kim ,  Moon-Sig Joo ,  Heung-Jae Cho ,  Won-Joon Choi

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/28247 ,  H01L27/10873

    摘要： A method of fabricating a semiconductor device includes forming a gate dielectric on a substrate, forming a gate structure on the gate dielectric, the gate structure comprising a stacked layer of a silicon layer and a metal layer, selectively etching the gate structure to form a gate pattern, forming a capping layer surrounding the gate pattern, plasma-treating the capping layer, and performing a gate reoxidation process

    摘要翻译： 制造半导体器件的方法包括在衬底上形成栅极电介质，在栅极电介质上形成栅极结构，栅极结构包括硅层和金属层的堆叠层，选择性地蚀刻栅极结构以形成栅极 形成围绕栅极图案的覆盖层，等离子体处理覆盖层，以及进行栅极再氧化工艺