公开(公告)号：US09335624B2

公开(公告)日：2016-05-10

申请号：US14277108

申请日：2014-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Yu Lee ,  Chi-Wen Chang ,  Chih Ming Yang ,  Ya Yun Liu ,  Yi-Kan Cheng

IPC: G06F17/50 ,  G03F1/00

CPC classification number: G03F1/00 ,  G03F1/144 ,  G03F1/70 ,  G03F7/70466 ,  G06F17/5068 ,  G06F17/5081

Abstract: A non-transitory, computer readable storage medium is encoded with computer program instructions, such that, when the computer program instructions are executed by a computer, the computer performs a method. The method generates mask assignment information for forming a plurality of patterns on a layer of an integrated circuit (IC) by multipatterning. The mask assignment information includes, for each of the plurality of patterns, a mask assignment identifying which of a plurality of masks is to be used to form that pattern, and a mask assignment lock state for that pattern. User inputs setting the mask assignment of at least one of the plurality of patterns, and its mask assignment lock state are received. A new mask assignment is generated for each of the plurality of patterns having an “unlocked” mask assignment lock state.

Abstract translation: 非暂时的计算机可读存储介质用计算机程序指令编码，使得当计算机程序指令由计算机执行时，计算机执行方法。 该方法通过多图案产生用于在集成电路（IC）的层上形成多个图案的掩模分配信息。 对于多个图案中的每一个，掩模分配信息包括识别多个掩模中哪一个要用于形成该图案的掩模分配以及该图案的掩模分配锁定状态。 用户输入设置多个图案中的至少一个的掩模分配以及其掩码分配锁定状态。 为具有“未锁定”掩码分配锁定状态的多个图案中的每一个生成新的掩模分配。

公开(公告)号：US08977991B2

公开(公告)日：2015-03-10

申请号：US14068006

申请日：2013-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huang-Yu Chen ,  Yuan-Te Hou ,  Chung-Min Fu ,  Chung-Hsing Wang ,  Wen-Hao Chen ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

Abstract translation: 接收到的布局标识要包括在集成电路（IC）层中的多个电路组件，用于使用两个光掩模对层进行双重图案化，所述布局包括要包括在第一光掩模中的多个第一图案和至少一个第二图案 被包括在第二个光掩模中。 所选择的第一模式中的一个具有第一和第二端点，被替换为将第一端点连接到第三端点的替换模式。 除了所选择的第一图案之外，至少一个相应的保留区域被设置为与每个相应的剩余第一图案相邻。 生成表示替换图案的数据，使得在任何保留区域中不形成替换图案的一部分。 输出表示剩余的第一图案和替换图案的数据。

公开(公告)号：US08645877B2

公开(公告)日：2014-02-04

申请号：US13902102

申请日：2013-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G03F1/70

Abstract: A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.

Abstract translation: 一种方法包括接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据。 该布局包括通过多图案化工艺在DPT层中形成的多个多边形。 分别使用第一和第二光掩模形成的多个多边形中的第一和第二多边形。 识别沿着连接第一多边形到第二多边形的第一路径以及沿着第一路径的相邻多边形之间的分隔区域的任何中间多边形。 分离器区域具有小于形成在第一光掩模上的多边形之间的最小阈值距离的尺寸。 计数分离器区域。 在将所述多个多边形中的所有剩余的多边形分配给第一或第二掩模之前，如果分离器区域的计数是偶数，则识别多图案化冲突。

公开(公告)号：US12230624B2

公开(公告)日：2025-02-18

申请号：US18232759

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou Sio ,  Jiann-Tyng Tzeng ,  Chung-Hsing Wang ,  Yi-Kan Cheng

IPC: H01L27/02 ,  H01L27/092 ,  G06F111/20

Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

公开(公告)号：US11923302B2

公开(公告)日：2024-03-05

申请号：US17854683

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-Yuan Chang ,  Noor Mohamed Ettuveettil ,  Po-Hsiang Huang ,  Sen-Bor Jan ,  Ming-Fa Chen ,  Chin-Chou Liu ,  Yi-Kan Cheng

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5286 ,  H01L23/5226 ,  H01L24/09 ,  H01L2224/08135 ,  H01L2224/08137 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/08147

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

公开(公告)号：US11769766B2

公开(公告)日：2023-09-26

申请号：US17585402

申请日：2022-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou Sio ,  Jiann-Tyng Tzeng ,  Chung-Hsing Wang ,  Yi-Kan Cheng

IPC: H01L27/02 ,  H01L27/092 ,  G06F111/20

CPC classification number: H01L27/0207 ,  H01L27/0924 ,  G06F2111/20

Abstract: An integrated circuit structure includes: an integrated circuit structure includes: a first plurality of cell rows extending in a first direction, and a second plurality of cell rows extending in the first direction. Each of the first plurality of cell rows has a first row height and comprises a plurality of first cells disposed therein. Each of the second plurality of cell rows has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction. The plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction. At least one active region of the first and second pluralities of active regions has a width varying along the first direction.

公开(公告)号：US11704472B2

公开(公告)日：2023-07-18

申请号：US17523600

申请日：2021-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung Chen ,  Jerry Chang-Jui Kao ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Shao-Huan Wang ,  XinYong Wang ,  Yi-Kan Cheng ,  Chun-Chen Chen

IPC: G06F30/00 ,  G06F30/398 ,  G06F30/394 ,  H01L27/02 ,  G06F111/04 ,  G06F30/18 ,  G06F119/18 ,  G06F111/20

CPC classification number: G06F30/398 ,  G06F30/394 ,  H01L27/0207 ,  G06F30/18 ,  G06F2111/04 ,  G06F2111/20 ,  G06F2119/18

Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

公开(公告)号：US10943729B2

公开(公告)日：2021-03-09

申请号：US16456025

申请日：2019-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ka Fai Chang ,  Chin-Chou Liu ,  Fong-Yuan Chang ,  Hui Yu Lee ,  Yi-Kan Cheng

IPC: H01L27/08 ,  H01F27/34 ,  H01F27/28 ,  H01F41/04 ,  H01L49/02 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48

Abstract: An entangled inductor structure generates opposite polarity internal magnetic fields therein to substantially reduce, or cancel, external magnetic fields propagating outside of the entangled inductor structure. These reduced external magnetic fields propagating outside of the entangled inductor structure effectively reduce a keep out zone (KOZ) between the entangled inductor structure and other electrical, mechanical, and/or electro-mechanical components. This allows the entangled inductor structure to be situated closer to these other electrical, mechanical, and/or electro-mechanical components within the IC as compared to conventional inductors which generate larger external magnetic fields.

公开(公告)号：US20190108304A1

公开(公告)日：2019-04-11

申请号：US16205441

申请日：2018-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Nan Yang ,  Chung-Hsing Wang ,  Yi-Kan Cheng ,  Kumar Lalgudi

IPC: G06F17/50 ,  H03K5/15 ,  H01L23/528

Abstract: In some embodiments, an initial circuit arrangement is provided. The initial circuit arrangement includes cells that include default-rule lines and non-default-rule lines. Line widths of the default-rule lines are selectively increased for a first cell in the initial circuit arrangement, thereby providing a first modified circuit arrangement. A first maximum capacitance value is calculated for the first cell of the first modified circuit arrangement. A second modified circuit arrangement is provided by selectively increasing line widths of the non-default-rule lines in the first modified circuit arrangement. A second maximum capacitance value is calculated for the first cell of the second modified circuit arrangement. A line width of a first non-default-rule line is selectively reduced based on whether the first maximum capacitance value adheres to a predetermined relationship with the second maximum capacitance value. The second modified circuit arrangement is manufactured on a semiconductor substrate.

公开(公告)号：US09026971B1

公开(公告)日：2015-05-05

申请号：US14148898

申请日：2014-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Lin Ho ,  Chin-Chang Hsu ,  Hung Lung Lin ,  Wen-Ju Yang ,  Yi-Kan Cheng ,  Tsong-Hua Ou ,  Wen-Li Cheng ,  Ken-Hsien Hsieh ,  Ching Hsiang Chang ,  Ting Yu Chen ,  Li-Chun Tien

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/70466 ,  G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present disclosure relates to a method and apparatus for forming a multiple patterning lithograph (MPL) compliant integrated circuit layout by operating a construction validation check on unassembled IC cells to enforce design restrictions that prevent MPL conflicts after assembly. In some embodiments, the method is performed by generating a plurality of unassembled integrated circuit (IC) cells having a multiple patterning design layer. A construction validation check is performed on the unassembled IC cells to identify violating IC cells having shapes disposed in patterns comprising potential multiple patterning coloring conflicts. Design shapes within a violating IC cell are adjusted to achieve a plurality of violation free IC cells. The plurality of violation free IC cells are then assembled to form an MPL compliant IC layout. Since the MPL compliant IC layout is free of coloring conflicts, a decomposition algorithm can be operated without performing a post assembly color conflict check.

Abstract translation: 本发明涉及一种用于通过对未组装的IC单元进行构造验证检查以形成在组装之后防止MPL冲突的设计限制来形成多重图案化平版印刷术（MPL）兼容集成电路布局的方法和装置。 在一些实施例中，该方法通过产生具有多个图案化设计层的多个未组装的集成电路（IC）单元来执行。 在未组装的IC细胞上进行结构验证检查，以识别具有以包含潜在的多个图案化着色冲突的图案布置的形状的违反IC细胞。 调整违规IC单元内的设计形状，以实现多个无冲突的IC单元。 然后组合多个违规免费IC电池以形成符合MPL的IC布局。 由于MPL兼容IC布局没有着色冲突，因此可以在不执行后期组合颜色冲突检查的情况下操作分解算法。