公开(公告)号：US20140282289A1

公开(公告)日：2014-09-18

申请号：US14210490

申请日：2014-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiung Hsu ,  Li-Chun Tien ,  Pin-Dai Sue ,  Ching Hsiang Chang ,  Wen-Hao Chen ,  Cheng-I Huang

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466

Abstract: A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern.

Abstract translation: 公开了一种确定单元布局的系统和方法。 所述方法包括接收与预定电路设计相对应的电路设计，所述电路设计具有第一组单元并邻接所述第一组单元中的相邻单元，所述邻接单元在其间具有第一边界图案。 基于第一边界图案中的信号线的数量或位置，第一边界图案与第二边界图案交换。 然后可以确定用于图案化处理的单元格布局，单元布局包括第二边界图案。

公开(公告)号：US09563731B2

公开(公告)日：2017-02-07

申请号：US14210490

申请日：2014-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiung Hsu ,  Li-Chun Tien ,  Pin-Dai Sue ,  Ching Hsiang Chang ,  Wen-Hao Chen ,  Cheng-I Huang

IPC: G06F17/50 ,  G03F7/20 ,  G03F1/70

CPC classification number: G06F17/5068 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466

Abstract: A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern.

Abstract translation: 公开了一种确定单元布局的系统和方法。 所述方法包括接收与预定电路设计相对应的电路设计，所述电路设计具有第一组单元并邻接所述第一组单元中的相邻单元，所述邻接单元在其间具有第一边界图案。 基于第一边界图案中的信号线的数量或位置，第一边界图案与第二边界图案交换。 然后可以确定用于图案化处理的单元格布局，单元布局包括第二边界图案。

公开(公告)号：US09026971B1

公开(公告)日：2015-05-05

申请号：US14148898

申请日：2014-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Lin Ho ,  Chin-Chang Hsu ,  Hung Lung Lin ,  Wen-Ju Yang ,  Yi-Kan Cheng ,  Tsong-Hua Ou ,  Wen-Li Cheng ,  Ken-Hsien Hsieh ,  Ching Hsiang Chang ,  Ting Yu Chen ,  Li-Chun Tien

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/70466 ,  G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present disclosure relates to a method and apparatus for forming a multiple patterning lithograph (MPL) compliant integrated circuit layout by operating a construction validation check on unassembled IC cells to enforce design restrictions that prevent MPL conflicts after assembly. In some embodiments, the method is performed by generating a plurality of unassembled integrated circuit (IC) cells having a multiple patterning design layer. A construction validation check is performed on the unassembled IC cells to identify violating IC cells having shapes disposed in patterns comprising potential multiple patterning coloring conflicts. Design shapes within a violating IC cell are adjusted to achieve a plurality of violation free IC cells. The plurality of violation free IC cells are then assembled to form an MPL compliant IC layout. Since the MPL compliant IC layout is free of coloring conflicts, a decomposition algorithm can be operated without performing a post assembly color conflict check.

Abstract translation: 本发明涉及一种用于通过对未组装的IC单元进行构造验证检查以形成在组装之后防止MPL冲突的设计限制来形成多重图案化平版印刷术（MPL）兼容集成电路布局的方法和装置。 在一些实施例中，该方法通过产生具有多个图案化设计层的多个未组装的集成电路（IC）单元来执行。 在未组装的IC细胞上进行结构验证检查，以识别具有以包含潜在的多个图案化着色冲突的图案布置的形状的违反IC细胞。 调整违规IC单元内的设计形状，以实现多个无冲突的IC单元。 然后组合多个违规免费IC电池以形成符合MPL的IC布局。 由于MPL兼容IC布局没有着色冲突，因此可以在不执行后期组合颜色冲突检查的情况下操作分解算法。