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公开(公告)号：US09122836B2
公开(公告)日：2015-09-01
申请号：US14251696
申请日：2014-04-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chung-Min Fu , Yung-Fong Lu , Wen-Ju Yang , Chin-Chang Hsu
CPC classification number: G06F17/5081 , G03F1/70
Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.
Abstract translation: 装置包括用于存储具有至少一个模板的模板库的机器可读存储介质。 该模板将包括通过多图案化IC的单层而形成的至少一个图案的第一布局图示。 该图案具有使用多个分别不同的光掩模形成的多个部分。 第一布局表示包括识别每个部分将要位于哪个光掩模上的数据。 电子设计自动化（EDA）工具包括被配置为接收电路的至少一部分的硬件描述语言表示并且生成具有多个多边形的电路的一部分的第二布局表示的处理器。 EDA工具具有匹配模块，其识别并输出多个部分中的一个或多个部分是否匹配多个多边形的子集的指示。
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公开(公告)号：US09038010B2
公开(公告)日：2015-05-19
申请号：US14058478
申请日：2013-10-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yao-Jen Chuang , Nien-Yu Tsai , Wen-Ju Yang
CPC classification number: G06F17/5081
Abstract: The present disclosure relates a method of performing a design rule checking (DRC) procedure on a multi-tiered integrated chip. In some embodiments, the method is performed by defining layer databases for a plurality of tiers within a multi-tiered integrated chip. The layer databases respectively identify design layers within an associated tier. A DRC (design rule checking) deck is then generated, which defines one or more individual design layer definitions as a function of a plurality of layer databases, so that the one or more individual design layer definitions are defined for a plurality of tiers. One or more design rules for the one or more individual design layer definitions are defined within the DRC deck. Since the individual design layer definitions are defined as functions of the plurality of layer databases, the design rules apply to the plurality of tiers.
Abstract translation: 本公开涉及在多层集成芯片上执行设计规则检查（DRC）过程的方法。 在一些实施例中，通过为多层集成芯片内的多个层定义层数据库来执行该方法。 层数据库分别标识相关层内的设计层。 然后生成DRC（设计规则检查）甲板，其定义作为多个层数据库的函数的一个或多个单独的设计层定义，从而为多个层定义一个或多个单独的设计层定义。 一个或多个单独的设计层定义的一个或多个设计规则在DRC平台内被定义。 由于各个设计层定义被定义为多个层数据库的功能，所以设计规则适用于多个层。
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公开(公告)号：US09471744B2
公开(公告)日：2016-10-18
申请号：US14819590
申请日：2015-08-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hung Lung Lin , Chin-Chang Hsu , Min-Yuan Tsai , Wen-Ju Yang , Chien Lin Ho
CPC classification number: G06F17/5081 , G03F7/0035 , G06F17/509
Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.
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公开(公告)号：US09223924B2
公开(公告)日：2015-12-29
申请号：US14043890
申请日：2013-10-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Hsiung Hsu , Chin-Chang Hsu , Yuan-Te Hou , Godina Ho , Wen-Hao Chen , Wen-Ju Yang
CPC classification number: G06F17/5081 , G03F1/00 , G03F1/36 , G03F1/70 , G03F7/70283 , G03F7/70466 , G06F17/5068 , G06F2217/12 , Y02P90/265
Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. A method for layout decomposition includes determining spacings between adjacent pairs of patterns, and generating a conflict graph having a plurality of sub-graphs, in which a respective vertex corresponds to each respective sub-graph. The patterns within each respective sub-graph are divided into at least a first group and a second group, each of which is assigned to be patterned on the single layer by a respectively different one of a first mask or a second mask. The method further include determining, in a processor, a count of color-rule violations in the plurality of patterns within each respective sub-graph based on a predetermined set of criteria; and within each sub-graph, assigning the first group of patterns in the sub-graph to the one of the first mask or the second mask which results in a smaller count of color-rule violations.
Abstract translation: 集成电路的单层布局的一部分是多图案化的。 用于布局分解的方法包括确定相邻图案对之间的间隔，以及生成具有多个子图的冲突图，其中相应的顶点对应于每个相应的子图。 每个相应子图中的图案被划分为至少第一组和第二组，其中的每一组被分配为通过第一掩模或第二掩模中的分别不同的一个在单层上被图案化。 该方法还包括在处理器中基于预定的一组标准来确定每个相应子图中的多个模式中的颜色规则违规的计数; 并且在每个子图中，将子图中的第一组图案分配给第一掩码或第二掩码中的一个，导致颜色规则违规的较小数量。
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公开(公告)号：US08645877B2
公开(公告)日：2014-02-04
申请号：US13902102
申请日：2013-05-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chang Hsu , Ying-Yu Shen , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng
IPC: G06F17/50
Abstract: A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.
Abstract translation: 一种方法包括接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据。 该布局包括通过多图案化工艺在DPT层中形成的多个多边形。 分别使用第一和第二光掩模形成的多个多边形中的第一和第二多边形。 识别沿着连接第一多边形到第二多边形的第一路径以及沿着第一路径的相邻多边形之间的分隔区域的任何中间多边形。 分离器区域具有小于形成在第一光掩模上的多边形之间的最小阈值距离的尺寸。 计数分离器区域。 在将所述多个多边形中的所有剩余的多边形分配给第一或第二掩模之前，如果分离器区域的计数是偶数，则识别多图案化冲突。
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Patent Agency Ranking
公开(公告)号：US09465901B2
公开(公告)日：2016-10-11
申请号：US14739108
申请日：2015-06-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Li-Sheng Ke , Jia-Rong Hsu , Hung-Lung Lin , Wen-Ju Yang
IPC: G06F17/00 , G06F17/50 , H01L29/66 , H01L21/8234 , H01L21/84 , H01L29/78 , H01L27/088
CPC classification number: G06F17/5072 , G06F2217/12 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L29/66795 , H01L29/6681 , H01L29/785 , Y02P90/265
Abstract: A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC.
Abstract translation: 方法实施例包括由处理器识别集成电路（IC）布局中的空区域，其中空区域是不包括任何活动鳍片的区域。 该方法还包括提供标准虚拟鳍片单元并形成扩展的虚拟鳍片单元。 标准虚拟鳍片单元包括多个隔板。 扩展的虚拟鳍片单元大于标准虚拟鳍片单元，并且扩展的虚拟鳍片单元包括多个分区中的每一个的整数倍。 空的区域填充有多个虚拟鳍片单元，其中多个虚拟鳍片单元包括扩展的虚拟鳍片单元。 多个虚拟鳍片单元在IC中实现。
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公开(公告)号：US20150278420A1
公开(公告)日：2015-10-01
申请号：US14739108
申请日：2015-06-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Li-Sheng Ke , Jia-Rong Hsu , Hung-Lung Lin , Wen-Ju Yang
IPC: G06F17/50
CPC classification number: G06F17/5072 , G06F2217/12 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L29/66795 , H01L29/6681 , H01L29/785 , Y02P90/265
Abstract: A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC.
Abstract translation: 方法实施例包括由处理器识别集成电路（IC）布局中的空区域，其中空区域是不包括任何活动鳍片的区域。 该方法还包括提供标准虚拟鳍片单元并形成扩展的虚拟鳍片单元。 标准虚拟鳍片单元包括多个隔板。 扩展的虚拟鳍片单元大于标准虚拟鳍片单元，并且扩展的虚拟鳍片单元包括多个分区中的每一个的整数倍。 空的区域填充有多个虚拟鳍片单元，其中多个虚拟鳍片单元包括扩展的虚拟鳍片单元。 多个虚拟鳍片单元在IC中实现。
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公开(公告)号：US09026971B1
公开(公告)日：2015-05-05
申请号：US14148898
申请日：2014-01-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chien Lin Ho , Chin-Chang Hsu , Hung Lung Lin , Wen-Ju Yang , Yi-Kan Cheng , Tsong-Hua Ou , Wen-Li Cheng , Ken-Hsien Hsieh , Ching Hsiang Chang , Ting Yu Chen , Li-Chun Tien
IPC: G06F17/50
CPC classification number: G06F17/5081 , G03F7/70466 , G06F17/5072 , G06F2217/12 , Y02P90/265
Abstract: The present disclosure relates to a method and apparatus for forming a multiple patterning lithograph (MPL) compliant integrated circuit layout by operating a construction validation check on unassembled IC cells to enforce design restrictions that prevent MPL conflicts after assembly. In some embodiments, the method is performed by generating a plurality of unassembled integrated circuit (IC) cells having a multiple patterning design layer. A construction validation check is performed on the unassembled IC cells to identify violating IC cells having shapes disposed in patterns comprising potential multiple patterning coloring conflicts. Design shapes within a violating IC cell are adjusted to achieve a plurality of violation free IC cells. The plurality of violation free IC cells are then assembled to form an MPL compliant IC layout. Since the MPL compliant IC layout is free of coloring conflicts, a decomposition algorithm can be operated without performing a post assembly color conflict check.
Abstract translation: 本发明涉及一种用于通过对未组装的IC单元进行构造验证检查以形成在组装之后防止MPL冲突的设计限制来形成多重图案化平版印刷术（MPL）兼容集成电路布局的方法和装置。 在一些实施例中，该方法通过产生具有多个图案化设计层的多个未组装的集成电路（IC）单元来执行。 在未组装的IC细胞上进行结构验证检查，以识别具有以包含潜在的多个图案化着色冲突的图案布置的形状的违反IC细胞。 调整违规IC单元内的设计形状，以实现多个无冲突的IC单元。 然后组合多个违规免费IC电池以形成符合MPL的IC布局。 由于MPL兼容IC布局没有着色冲突，因此可以在不执行后期组合颜色冲突检查的情况下操作分解算法。
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公开(公告)号：US20150113489A1
公开(公告)日：2015-04-23
申请号：US14058478
申请日：2013-10-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yao-Jen Chuang , Nien-Yu Tsai , Wen-Ju Yang
IPC: G06F17/50
CPC classification number: G06F17/5081
Abstract: The present disclosure relates a method of performing a design rule checking (DRC) procedure on a multi-tiered integrated chip. In some embodiments, the method is performed by defining layer databases for a plurality of tiers within a multi-tiered integrated chip. The layer databases respectively identify design layers within an associated tier. A DRC (design rule checking) deck is then generated, which defines one or more individual design layer definitions as a function of a plurality of layer databases, so that the one or more individual design layer definitions are defined for a plurality of tiers. One or more design rules for the one or more individual design layer definitions are defined within the DRC deck. Since the individual design layer definitions are defined as functions of the plurality of layer databases, the design rules apply to the plurality of tiers.
Abstract translation: 本公开涉及在多层集成芯片上执行设计规则检查（DRC）过程的方法。 在一些实施例中，通过为多层集成芯片内的多个层定义层数据库来执行该方法。 层数据库分别标识相关层内的设计层。 然后生成DRC（设计规则检查）甲板，其定义作为多个层数据库的函数的一个或多个单独的设计层定义，从而为多个层定义一个或多个单独的设计层定义。 一个或多个单独的设计层定义的一个或多个设计规则在DRC平台内被定义。 由于各个设计层定义被定义为多个层数据库的功能，所以设计规则适用于多个层。
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公开(公告)号：US09122838B2
公开(公告)日：2015-09-01
申请号：US14302684
申请日：2014-06-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hung Lung Lin , Chin-Chang Hsu , Min-Yuan Tsai , Wen-Ju Yang , Chien Lin Ho
CPC classification number: G06F17/5081 , G03F7/0035 , G06F17/509
Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.
Abstract translation: 提供了一种用于在半导体制造中评估和分解用于三重图案光刻的半导体器件电平的方法。 该方法包括使用各种方法生成冲突图并简化冲突图，以产生可以进一步简化或评估分解有效性的简化冲突图。 本公开还提供将分解有效性规则应用于简化的冲突图，以确定冲突图是否表示可分解成三个掩模的半导体器件层。 公开的方法由计算机执行，并且用于执行该方法的指令可以存储在计算机可读存储介质上。
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