公开(公告)号：US20250014943A1

公开(公告)日：2025-01-09

申请号：US18219259

申请日：2023-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zheng Yong LIANG ,  Wei-Ting YEH ,  I-Han HUANG ,  Chen-Hao WU ,  An-Hsuan LEE ,  Huang-Lin CHAO ,  Yu-Yun PENG ,  Keng-Chu LIN

IPC: H01L21/768 ,  H01L21/3105 ,  H01L23/00 ,  H01L29/66

Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.

公开(公告)号：US20240332419A1

公开(公告)日：2024-10-03

申请号：US18736207

申请日：2024-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Yun PENG ,  Keng-Chu LIN

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/02142 ,  H01L21/02148 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/308 ,  H01L21/76283 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L21/02145 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76837 ,  H01L29/7843

Abstract: A device includes a semiconductive substrate, a fin structure, and an isolation material. The fin structure extends from the semiconductive substrate. The isolation material is over the semiconductive substrate and adjacent to the fin structure, wherein the isolation material includes a first metal element, a second metal element, and oxide.

公开(公告)号：US20240249947A1

公开(公告)日：2024-07-25

申请号：US18434553

申请日：2024-02-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Yun PENG ,  Chung-Chi KO ,  Keng-Chu LIN

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/28158 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/76224

Abstract: A device includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first conductor is in the first dielectric layer. The etch stop layer is over the first dielectric layer. The etch stop layer has a first surface facing the first dielectric layer and a second surface facing away from the first dielectric layer, and a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. The second dielectric layer is over the etch stop layer. The second conductor is in the second dielectric layer and the etch stop layer and electrically connected to the first conductor.

公开(公告)号：US20230395683A1

公开(公告)日：2023-12-07

申请号：US17833803

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuei-Lin CHAN ,  Fu-Ting YEN ,  Yu-Yun PENG ,  Keng-Chu LIN

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/66795 ,  H01L29/0669 ,  H01L21/30604 ,  H01L21/0226 ,  H01L29/78687

Abstract: A post-deposition treatment can be applied to an atomic layer deposition (ALD)-deposited film to seal one or more seams at the surface. The seam-top treatment can physically merge the two sides of the seam, so that the surface behaves as a continuous material to allow etching at a substantially uniform rate across the surface of the film. The seam-top treatment can be used to merge seams in ALD-deposited films within semiconductor structures, such as gate-all-around field effect transistors (GAAFETs).

公开(公告)号：US20230387254A1

公开(公告)日：2023-11-30

申请号：US18446674

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN ,  Yu-Yun PENG

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/66553 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4991 ,  H01L29/78618 ,  H01L29/66742 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31116 ,  H01L29/6653 ,  H01L29/66545 ,  H01L21/02603 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/31111 ,  H01L27/0886 ,  H01L21/823481 ,  H01L21/0234

Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.

公开(公告)号：US20230068065A1

公开(公告)日：2023-03-02

申请号：US17461271

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Sathaiya Mahaveer DHANYAKUMAR ,  Huicheng CHANG ,  Keng-Chu LIN ,  Winnie Victoria Wei-Ning CHEN

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/092

Abstract: A semiconductor device includes a first transistor device of a first type. The first transistor includes first nanostructures, a first pair of source/drain structures, and a first gate electrode on the first nanostructures. The semiconductor device also includes a second transistor device of a second type formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate electrode on the second nanostructures and over the first nanostructures. The semiconductor device also includes a first isolation structure between the first and second nanostructures. The semiconductor device further includes a second isolation structure in contact with a top surface of the first pair of source/drain structures. The semiconductor device also includes a seed layer between the second isolation structure and the second pair of source/drain structures.

公开(公告)号：US20230016100A1

公开(公告)日：2023-01-19

申请号：US17815730

申请日：2022-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Kai CHANG ,  Keng-Chu LIN ,  Sung-Li WANG ,  Shuen-Shin LIANG ,  Chia-Hung CHU

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

公开(公告)号：US20230009144A1

公开(公告)日：2023-01-12

申请号：US17591413

申请日：2022-02-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hung LIN ,  Ko-Feng CHEN ,  Keng-Chu LIN

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/306 ,  H01L21/762

Abstract: A semiconductor device with densified dielectric structures and a method of fabricating the same are disclosed. The method includes forming a fin structure, forming an isolation structure adjacent to the fin structure, forming a source/drain (S/D) region on the fin structure, depositing a flowable dielectric layer on the isolation structure, converting the flowable dielectric layer into a non-flowable dielectric layer, performing a densification process on the non-flowable dielectric layer, and repeating the depositing, converting, and performing to form a stack of densified dielectric layers surrounding the S/D region.

公开(公告)号：US20220139773A1

公开(公告)日：2022-05-05

申请号：US17575444

申请日：2022-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li WANG ,  Shuen-Shin LIANG ,  Yu-Yun PENG ,  Fang-Wei LEE ,  Chia-Hung CHU ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC: H01L21/768 ,  H01L21/306 ,  H01L23/522 ,  H01L21/285 ,  H01L21/02 ,  H01L23/532

Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.

公开(公告)号：US20210202715A1

公开(公告)日：2021-07-01

申请号：US17200226

申请日：2021-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Lun CHENG ,  Chih-Hao WANG ,  Keng-Chu LIN ,  Shi-Ning JU

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, a gate structure, a plurality of source/drain structures, a shallow trench isolation (STI) oxide, and a dielectric layer. The first semiconductor fin extends upwardly from the substrate. The second semiconductor fin extends upwardly from the substrate. The gate structure extends across the first and second semiconductor fins. The source/drain structures are on the first and second semiconductor fins. The STI oxide extends continuously between the first and second semiconductor fins and has a U-shaped profile when viewed in a cross section taken along a lengthwise direction of the gate structure. The dielectric layer is partially embedded in the STI oxide and has a U-shaped profile when viewed in the cross section taken along the lengthwise direction of the gate structure.