公开(公告)号：US20230066230A1

公开(公告)日：2023-03-02

申请号：US17412896

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Yun PENG ,  Fu-Ting YEN ,  Keng-Chu LIN

IPC: H01L29/66 ,  H01L29/06

Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.

公开(公告)号：US20220359202A1

公开(公告)日：2022-11-10

申请号：US17871659

申请日：2022-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei SU ,  Fu-Ting YEN ,  Teng-Chun TSAI

IPC: H01L21/033 ,  H01L21/768 ,  H01L29/40 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321

Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; performing a plasma treatment to a first portion of the dielectric layer, such that a carbon concentration of the first portion of the dielectric layer is lower than a carbon concentration of a second portion of the dielectric layer; selectively forming an inhibitor over the first portion of the dielectric layer; and selectively forming a hard mask over portions of the metal layer that is uncovered by the inhibitor.

公开(公告)号：US20230395683A1

公开(公告)日：2023-12-07

申请号：US17833803

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuei-Lin CHAN ,  Fu-Ting YEN ,  Yu-Yun PENG ,  Keng-Chu LIN

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L21/306 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/66795 ,  H01L29/0669 ,  H01L21/30604 ,  H01L21/0226 ,  H01L29/78687

Abstract: A post-deposition treatment can be applied to an atomic layer deposition (ALD)-deposited film to seal one or more seams at the surface. The seam-top treatment can physically merge the two sides of the seam, so that the surface behaves as a continuous material to allow etching at a substantially uniform rate across the surface of the film. The seam-top treatment can be used to merge seams in ALD-deposited films within semiconductor structures, such as gate-all-around field effect transistors (GAAFETs).

公开(公告)号：US20210287904A1

公开(公告)日：2021-09-16

申请号：US17333639

申请日：2021-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei SU ,  Fu-Ting YEN ,  Ting-Ting CHEN ,  Teng-Chun TSAI

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3205

Abstract: A method includes forming a gate structure and an interlayer dielectric (ILD) layer over a substrate; selectively forming an inhibitor over the gate structure; performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD layer, wherein in the ALD process the dielectric layer has greater growing rate on the ILD than on the inhibitor; and performing an atomic layer etching (ALE) process to etch the dielectric layer until a top surface of the inhibitor is exposed, in which a portion of the dielectric layer remains on the ILD layer after the ALE process is complete.

公开(公告)号：US20230146366A1

公开(公告)日：2023-05-11

申请号：US18152952

申请日：2023-01-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei SU ,  Fu-Ting YEN ,  Ting-Ting CHEN ,  Teng-Chun TSAI

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3205

CPC classification number: H01L21/28088 ,  H01L21/28079 ,  H01L21/32135 ,  H01L21/02118 ,  H01L29/6656 ,  H01L21/31116 ,  H01L21/02282 ,  H01L21/0206 ,  H01L21/28556 ,  H01L21/31058 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/32051 ,  H01L29/66795 ,  H01L21/32

Abstract: A device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, source/drain structures over the substrate and on opposite sides of the gate structure, and a self-assemble monolayer (SAM) in contact with an inner sidewall of one of the gate spacer and in contact with a top surface of the gate structure.

公开(公告)号：US20230141093A1

公开(公告)日：2023-05-11

申请号：US18149130

申请日：2023-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu LIN ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Tzer-Min SHEN ,  Fu-Ting YEN ,  Gary CHAN ,  Keng-Chu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/8234 ,  H01L21/3065

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L21/823418

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

公开(公告)号：US20190164758A1

公开(公告)日：2019-05-30

申请号：US16037925

申请日：2018-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei SU ,  Fu-Ting YEN ,  Teng-Chun TSAI

IPC: H01L21/033 ,  H01L29/40 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/768

Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; removing a first portion of the dielectric layer to expose a first portion of the metal layer, while a second portion of the dielectric layer remains on the metal layer; selectively forming a first inhibitor on the second portion of the dielectric layer, while the metal layer is free of coverage by the first inhibitor; and selectively depositing a first hard mask on the exposed first portion of the metal layer, while the first inhibitor is free of coverage by the first hard mask.

公开(公告)号：US20230009820A1

公开(公告)日：2023-01-12

申请号：US17591416

申请日：2022-02-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Ting YEN ,  Wei-Ting YEH ,  Shih-Cheng CHEN ,  Yu-Yun PENG

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a source/drain (S/D) opening in the superlattice structure, forming an isolation opening in the fin structure and below the S/D opening, forming a first isolation layer in the isolation opening, selectively forming an oxide layer on sidewalls of the S/D opening, selectively forming an inhibitor layer on the oxide layer, selectively depositing a second isolation layer on the first isolation layer, and forming S/D regions in the S/D opening on the second isolation layer.

公开(公告)号：US20200373160A1

公开(公告)日：2020-11-26

申请号：US16988635

申请日：2020-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei SU ,  Fu-Ting YEN ,  Teng-Chun TSAI

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3205 ,  H01L21/768 ,  H01L29/40

Abstract: A method includes forming a metal layer over a substrate; forming a dielectric layer over the metal layer; removing a first portion of the dielectric layer to expose a first portion of the metal layer, while a second portion of the dielectric layer remains on the metal layer; selectively forming a first inhibitor on the second portion of the dielectric layer, while the metal layer is free of coverage by the first inhibitor; and selectively depositing a first hard mask on the exposed first portion of the metal layer, while the first inhibitor is free of coverage by the first hard mask.

公开(公告)号：US20190164762A1

公开(公告)日：2019-05-30

申请号：US16122235

申请日：2018-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei SU ,  Fu-Ting YEN ,  Ting-Ting CHEN ,  Teng-Chun TSAI

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/285 ,  H01L21/3105

Abstract: A method includes forming a gate stack and an interlayer dielectric (ILD) over a substrate, wherein the interlayer dielectric is adjacent to the gate stack; forming an inhibitor covering the interlayer dielectric such that the gate stack is exposed from the inhibitor; performing a deposition process to form a conductive layer over the gate stack until the conductive layer starts to form on the inhibitor, in which the deposition process has a deposition selectivity for the gate stack with respect to the inhibitor; and performing an etching process to remove a portion of the conductive layer over the inhibitor.