公开(公告)号：US09684236B1

公开(公告)日：2017-06-20

申请号：US15073073

申请日：2016-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ken-Hsien Hsieh ,  Kuan-Hsin Lo ,  Shih-Ming Chang ,  Wei-Liang Lin ,  Joy Cheng ,  Chun-Kuang Chen ,  Ching-Yu Chang ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Chin-Hsiang Lin

IPC: G03F7/11 ,  G03F7/40 ,  G03F7/00 ,  H01L21/308 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3213 ,  G03F7/20 ,  G03F7/16 ,  G03F7/32 ,  H01L21/027 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3065

CPC classification number: G03F7/002 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/165 ,  G03F7/20 ,  G03F7/2022 ,  G03F7/2059 ,  G03F7/32 ,  G03F7/40 ,  H01L21/02112 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3086

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first patterned hard mask over a material layer. The first patterned hard mask defines an opening. The method also includes forming a direct-self-assembly (DSA) layer having a first portion and a second portion within the opening, removing the first portion of the DSA layer, forming spacers along sidewalls of the second portion of the DSA layer and removing the second portion of the DSA layer. The spacers form a second patterned hard mask over the material layer.

公开(公告)号：US20150076371A1

公开(公告)日：2015-03-19

申请号：US14551302

申请日：2014-11-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

IPC: H01L21/67 ,  H01J37/20 ,  H01J37/16 ,  H01J37/32 ,  H01J37/317

CPC classification number: H01L21/67225 ,  G03F7/16 ,  G03F7/30 ,  G03F7/70991 ,  H01J37/16 ,  H01J37/20 ,  H01J37/3174 ,  H01J37/32899 ,  H01L21/67276 ,  H01L21/67745

Abstract: The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

Abstract translation: 本公开涉及一种用于半导体工件加工的平版印刷工具装置。 光刻工具装置将光刻工具组合成簇，并且将半导体工件在第一簇中的第一类型的多个光刻工具之间选择性地传输到第二簇中的第二类型的光刻工具。 通过转移组件实现选择性转移，转移组件耦合到识别第一类型的光刻工具中产生的缺陷的缺陷扫描工具。 所公开的平版印刷工具装置还利用共同的结构元件，例如壳体组件和诸如气体和化学品的共享功能元件。 光刻工具装置可以包括被配置成提供这些各种部件的模块化的烘烤，涂覆，曝光和显影单元，以便为给定的光刻制造工艺优化产量和效率。

公开(公告)号：US20140100684A1

公开(公告)日：2014-04-10

申请号：US13647643

申请日：2012-10-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Chun-Hsien Lin ,  Jui-Long Chen ,  Hui-Yun Chao ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC: G06F19/00

CPC classification number: G06F17/50 ,  G03F7/70533 ,  G03F7/70616 ,  G05B23/024

Abstract: A method for analyzing abnormalities in a semiconductor processing system provides performing an analysis of variance on a production history associated with each of a plurality of tools at each of a plurality of process steps for each of a plurality of processed wafers, and key process steps are identified. A regression analysis on a plurality of measurements of the plurality of wafers at each process step is performed and key measurement parameters are identified. An analysis of covariance on the key measurement parameters and key process steps, and the key process steps are ranked based on an f-ratio, therein ranking an abnormality of the key process steps. Further, the plurality of tools associated with each of the key process steps are ranked based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps.

Abstract translation: 一种用于分析半导体处理系统中的异常的方法，提供了在多个处理晶片中的每一个的多个处理步骤中的每一个处执行与多个工具中的每一个相关联的生产历史上的方差分析，并且关键处理步骤 确定。 执行在每个处理步骤对多个晶片的多个测量的回归分析，并且识别关键测量参数。 关键测量参数和关键过程步骤的协方差分析以及关键过程步骤基于f比进行排序，其中排列关键过程步骤的异常。 此外，与关键处理步骤中的每一个相关联的多个工具基于与协方差分析相关联的正交t比进行排序，其中对与关键处理步骤相关联的每个工具进行排序。

公开(公告)号：US12154822B2

公开(公告)日：2024-11-26

申请号：US18302428

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Keng-Chu Lin ,  Shwang-Ming Jeng ,  Teng-Chun Tsai ,  Tsu-Hsiu Perng ,  Fu-Ting Yen

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

公开(公告)号：US20240377731A1

公开(公告)日：2024-11-14

申请号：US18779265

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Joy Cheng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/004 ,  G03F7/30 ,  G03F7/32 ,  G03F7/36

Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a metal-containing chemical; performing an exposing process to the photoresist layer; and performing a first developing process to the photoresist layer using a first developer, thereby forming a patterned resist layer, wherein the first developer includes a first solvent and a chemical additive to remove metal residuals generated from the metal-containing chemical.

公开(公告)号：US12087861B2

公开(公告)日：2024-09-10

申请号：US17814681

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Tai-Chun Huang ,  Tien-I Bao

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/033 ,  H01L21/768 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7851 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76843 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/5283 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878

Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.

公开(公告)号：US11822238B2

公开(公告)日：2023-11-21

申请号：US17121080

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Joy Cheng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/004 ,  G03F7/32 ,  G03F7/30 ,  G03F7/36

CPC classification number: G03F7/0042 ,  G03F7/0047 ,  G03F7/32 ,  G03F7/325 ,  G03F7/30 ,  G03F7/36

Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a metal-containing chemical; performing an exposing process to the photoresist layer; and performing a first developing process to the photoresist layer using a first developer, thereby forming a patterned resist layer, wherein the first developer includes a first solvent and a chemical additive to remove metal residuals generated from the metal-containing chemical.

公开(公告)号：US11809080B2

公开(公告)日：2023-11-07

申请号：US17816004

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Han Lai ,  Chin-Hsiang Lin ,  Chien-Wei Wang

IPC: G03F7/004 ,  G03F7/039 ,  C07D247/02 ,  C07D273/00

CPC classification number: G03F7/0397 ,  C07D247/02 ,  G03F7/0045 ,  G03F7/0046 ,  G03F7/0392 ,  C07D273/00 ,  G03F7/0042

Abstract: A method includes forming a photoresist layer over a substrate, wherein the photoresist layer includes a polymer, a sensitizer, and a photo-acid generator (PAG), wherein the sensitizer includes a resonance ring that includes nitrogen and at least one double bond. The method further includes performing an exposing process to the photoresist layer. The method further includes developing the photoresist layer, thereby forming a patterned photoresist layer.

公开(公告)号：US20230253240A1

公开(公告)日：2023-08-10

申请号：US18302428

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Keng-Chu Lin ,  Shwang-Ming Jeng ,  Teng-Chun Tsai ,  Tsu-Hsiu Perng ,  Fu-Ting Yen

IPC: H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L21/76229 ,  H01L21/823878 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/66545 ,  H01L29/785 ,  H01L21/823892 ,  H01L29/6681 ,  H01L21/823431

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

公开(公告)号：US11605538B2

公开(公告)日：2023-03-14

申请号：US16655089

申请日：2019-10-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： An-Ren Zi ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  G03F7/038 ,  G03F1/22

Abstract: A method includes forming protective layer over substrate edge and photoresist over substrate. Protective layer removed and photoresist exposed to radiation. Protective layer made of composition including acid generator and polymer having pendant acid-labile groups. Pendant acid-labile groups include polar functional groups; acid-labile groups including polar switch functional groups; acid-labile groups, wherein greater than 5% of pendant acid-labile groups have structure wherein R1 is C6-C30 alkyl group, cycloalkyl group, hydroxylalkyl group, alkoxy group, alkoxyl alkyl group, acetyl group, acetylalkyl group, carboxyl group, alkyl carboxyl group, cycloalkyl carboxyl group, saturated or unsaturated hydrocarbon ring, or heterocyclic group; and R2 is C4-C9 alkyl group, cycloalkyl group, hydroxylalkyl group, alkoxy group, alkoxyl alkyl group, acetyl group, acetylalkyl group, carboxyl group, alkyl carboxyl group, or cycloalkyl carboxyl group; polymer having pendant acid-labile groups and lactone pendant groups; or polymer having pendant acid-labile groups and carboxylic acid groups.