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公开(公告)号：US09627365B1
公开(公告)日：2017-04-18
申请号：US15007714
申请日：2016-01-27
Inventor： Chen-Hua Yu , Shang-Yun Hou , Yun-Han Lee
IPC: H01L29/00 , H01L25/10 , H01L23/522
CPC classification number: H01L24/97 , G05F3/02 , H01L21/4846 , H01L23/28 , H01L23/481 , H01L23/5226 , H01L23/5227 , H01L23/5389 , H01L24/25 , H01L25/0652 , H01L25/105 , H01L27/0688 , H01L27/124 , H01L27/2481 , H01L27/283 , H01L28/10 , H01L2224/16225 , H01L2225/0651 , H01L2225/06541 , H01L2225/06582 , H01L2225/1041 , H01L2225/1058 , H01L2225/107
Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
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公开(公告)号：US11727177B2
公开(公告)日：2023-08-15
申请号：US17836954
申请日：2022-06-09
Inventor： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC: G06F30/327 , G06F30/398 , G06F30/333 , G06F30/3308 , G06F119/18 , G06F119/02
CPC classification number: G06F30/327 , G06F30/398 , G06F30/333 , G06F30/3308 , G06F2119/02 , G06F2119/18
Abstract: A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a unique dominant feature among a plurality of features of the plurality of paths. The dominant feature of a group among the plurality of groups is slack. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.
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公开(公告)号：US11699010B2
公开(公告)日：2023-07-11
申请号：US17365468
申请日：2021-07-01
Inventor： Sandeep Kumar Goel , Ankita Patidar , Yun-Han Lee
IPC: G06F30/323 , G06F30/3323 , G06F30/392 , G06F30/394 , G03F1/70 , G06F119/12
CPC classification number: G06F30/323 , G03F1/70 , G06F30/3323 , G06F30/392 , G06F30/394 , G06F2119/12
Abstract: A method of manufacturing a semiconductor device includes reducing errors in a migration of a first netlist to a second netlist, the first netlist corresponding to a first semiconductor process technology (SPT), the second first netlist corresponding to a second SPT, the first and second netlists each representing a same circuit design, the reducing errors including: inspecting a timing constraint list corresponding to the second netlist for addition candidates; generating a first version of the second netlist having a first number of comparison points relative to a logic equivalence check (LEC) context, the first number of comparison points being based on the addition candidates; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.
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公开(公告)号：US11687454B2
公开(公告)日：2023-06-27
申请号：US17568199
申请日：2022-01-04
Inventor： Hsien-Hsin Sean Lee , William Wu Shen , Yun-Han Lee
IPC: G11C7/00 , G06F12/0804 , G11C5/04 , G11C5/02 , G06F12/0891 , G11C7/22
CPC classification number: G06F12/0804 , G06F12/0891 , G11C5/025 , G11C5/04 , G11C7/22 , G06F2212/1008 , G06F2212/1032 , G06F2212/45 , G06F2212/608 , H01L2224/16225 , H01L2924/15311
Abstract: A memory circuit includes a stack of first dies including multiple sets of memory cells of a first type, a second die including multiple sets of memory cells of a second type, a third die, and an interposer carrying the first, second, and third dies. The second die includes a first set of input/output (I/O) terminals on a top surface of the second die and a second set of I/O terminals on a bottom surface of the second die. The stack of first dies is coupled to the second die through the first set of I/O terminals. The interposer is coupled to the second die through the second set of I/O terminals. The third die is positioned aside the second die and in communication with the second die through the interposer.
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公开(公告)号：US11632048B2
公开(公告)日：2023-04-18
申请号：US16799327
申请日：2020-02-24
Inventor： Haohua Zhou , Tze-Chiang Huang , Mei Hsu , Yun-Han Lee
Abstract: A voltage regulator includes an output node, a control circuit, and a power stage. The control circuit is configured to receive a power state signal from a load circuit coupled to the output node, and output a control signal based on the power state signal. The power stage includes a plurality of phase circuits coupled to the output node and is configured to enable a phase circuit of the plurality of phase circuits responsive to the control signal.
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Patent Agency Ranking
公开(公告)号：US11616631B2
公开(公告)日：2023-03-28
申请号：US15931273
申请日：2020-05-13
Inventor： Huan-Neng Chen , William Wu Shen , Chewn-Pu Jou , Feng Wei Kuo , Lan-Chou Cho , Tze-Chiang Huang , Jack Liu , Yun-Han Lee
Abstract: An integrated circuit includes a first through fourth devices positioned over a substrate, the first device including first through third transceivers, the second device including a fourth transceiver, the third device including a fifth transceiver, and the fourth device including a sixth transceiver. A first radio frequency interconnect (RFI) includes the first transceiver coupled to the fourth transceiver through a first guided transmission medium, a second RFI includes the second transceiver coupled to the fifth transceiver through a second guided transmission medium, and a third RFI includes the third transceiver coupled to the sixth transceiver by the second guided transmission medium.
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公开(公告)号：US11496417B2
公开(公告)日：2022-11-08
申请号：US16879567
申请日：2020-05-20
Inventor： Ravi Venugopalan , Sandeep Kumar Goel , Yun-Han Lee
IPC: H04L49/109 , H04L45/00 , H04L45/28
Abstract: A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path is configured to replace the default communication path when a fault arises in the default communication path.
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公开(公告)号：US11386253B2
公开(公告)日：2022-07-12
申请号：US16901641
申请日：2020-06-15
Inventor： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC: G06F30/333 , G01R31/3185 , G01R31/317 , G06F30/00
Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.
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公开(公告)号：US11379643B2
公开(公告)日：2022-07-05
申请号：US17122769
申请日：2020-12-15
Inventor： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC: G06F30/327 , G06F30/398 , G06F30/3308 , G06F30/333 , G06F119/18 , G06F119/02
Abstract: A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a dominant feature among a plurality of features of the plurality of paths. The dominant features of the plurality of groups are different from each other. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.
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公开(公告)号：US20220129382A1
公开(公告)日：2022-04-28
申请号：US17568199
申请日：2022-01-04
Inventor： Hsien-Hsin Sean Lee , William Wu Shen , Yun-Han Lee
IPC: G06F12/0804 , G11C5/04 , G11C5/02 , G06F12/0891 , G11C7/22
Abstract: A memory circuit includes a stack of first dies including multiple sets of memory cells of a first type, a second die including multiple sets of memory cells of a second type, a third die, and an interposer carrying the first, second, and third dies. The second die includes a first set of input/output (I/O) terminals on a top surface of the second die and a second set of I/O terminals on a bottom surface of the second die. The stack of first dies is coupled to the second die through the first set of I/O terminals. The interposer is coupled to the second die through the second set of I/O terminals. The third die is positioned aside the second die and in communication with the second die through the interposer.
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