公开(公告)号：US09431351B2

公开(公告)日：2016-08-30

申请号：US14517026

申请日：2014-10-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Guan-Yu Chen ,  Yu-Wei Lin ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498 ,  H01L21/66

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L22/12 ,  H01L22/20 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17106 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a predetermined temperature range; (2) determining a difference between a density of a top metal and a density of a bottom metal of a substrate according to the die warpage value; and (3) joining the die and the substrate under the predetermined temperature range. The top metal includes all metal layers overlying a middle layer, and the bottom metal includes all metal layers underlying the middle layer. The middle layer includes a core or a metal layer.

Abstract translation: 本公开提供了一种用于制造半导体封装的方法。 该方法包括（1）在预定温度范围内确定模翘曲值; （2）根据所述模具翘曲值确定顶部金属的密度与基板的底部金属的密度之间的差异; 和（3）在规定的温度范围内连接管芯和基板。 顶部金属包括覆盖中间层的所有金属层，底部金属包括中间层下面的所有金属层。 中间层包括芯或金属层。

公开(公告)号：US09236877B2

公开(公告)日：2016-01-12

申请号：US14106962

申请日：2013-12-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yung-Chow Peng ,  Wen-Hung Huang ,  Yu-Wei Lin

IPC: H03M1/12 ,  H03M1/00 ,  B81B7/00 ,  H03M3/00

CPC classification number: H03M1/002 ,  B81B7/008 ,  H03M1/0626 ,  H03M1/12 ,  H03M3/30

Abstract: A micro-electro-mechanical system (MEMS) includes a micro-mechanical structure that generates a first electrical signal. An analog-to-digital converter (ADC) is coupled with the micro-mechanical structure. The first electrical signal is converted to a second electrical signal using a converter coupled between the micro-mechanical structure and the ADC. The first electrical signal is free from being amplified.

Abstract translation: 微机电系统（MEMS）包括产生第一电信号的微机械结构。 模数转换器（ADC）与微机械结构耦合。 使用耦合在微机械结构和ADC之间的转换器将第一电信号转换成第二电信号。 第一个电信号没有被放大。

公开(公告)号：US20150380332A1

公开(公告)日：2015-12-31

申请号：US14845799

申请日：2015-09-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Lin ,  Guan-Yu Chen ,  Yu-Min Liang ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H05K1/18

CPC classification number: H01L23/562 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16013 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3841 ,  H05K1/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.

公开(公告)号：US20150194379A1

公开(公告)日：2015-07-09

申请号：US14456812

申请日：2014-08-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Shien Chen ,  Yu-Feng Chen ,  Yu-Wei Lin ,  Tin-Hao Kuo ,  Yu-Min Liang ,  Chun-Hung Lin

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L24/16 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81

Abstract: An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2

Abstract translation: 一种实施方式的装置包括：管芯中的电介质层，电介质层中的导电迹线，以及导电迹线上的突起焊盘。 突起凸块至少部分地延伸在电介质层上，并且突起凸块垫包括纵向轴线和宽度方向轴线。 纵向轴线的第一尺寸与宽度方向轴线的第二尺寸的比率为约0.8至约1.2

公开(公告)号：US20140077360A1

公开(公告)日：2014-03-20

申请号：US13744361

申请日：2013-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Wei Lin ,  Sheng-Yu Wu ,  Yu-Jen Tseng ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

Abstract translation: 轨迹（BOT）结构上的实施例凸点包括由集成电路支撑的接触元件，电耦合到接触元件的凸块下冶金（UBM）特征，安装在凸块下金属特征上的金属梯形凸起，金属梯形凸起 具有第一锥形轮廓和安装在基底上的基底迹线，所述基底迹线具有第二锥形轮廓，并通过直接的金属 - 金属接合耦合到所述金属梯形凸起。 可以以类似的方式制造实施例的芯片到芯片结构。

公开(公告)号：US20140077358A1

公开(公告)日：2014-03-20

申请号：US13712722

申请日：2012-12-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guan-Yu Chen ,  Yu-Wei Lin ,  Yu-Jen Tseng ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Abstract translation: 轨迹（BOT）结构上的实施例凸块包括由集成电路支撑的接触元件，电耦合到接触元件的凸块下金属（UBM）特征，凸起下金属冶金特征上的金属凸块，以及衬底迹线 衬底，通过焊接接头和金属间化合物耦合到金属凸块的衬底迹线，金属间化合物的第一横截面积与焊料接头的第二横截面积的比率大于百分之四十。