公开(公告)号：US09536790B2

公开(公告)日：2017-01-03

申请号：US14154618

申请日：2014-01-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Amit Kundu ,  Jaw-Juinn Horng ,  Chung-Hui Chen

IPC: H01L29/76 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/78 ,  H01L27/12 ,  H01L23/367

CPC classification number: H01L23/367 ,  H01L21/761 ,  H01L21/823431 ,  H01L23/3677 ,  H01L27/0248 ,  H01L27/0292 ,  H01L27/1211 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device comprises a substrate, a source region over the substrate, and a guard ring over the substrate. The guard ring is separated from the source region by a first spacing. The semiconductor device also comprises a first heat conductive layer formed over couples the source region and the guard ring. The semiconductor device further comprises a first via over a first portion of the first heat conductive layer. The semiconductor device additionally comprises a second via separate from the first via over a second portion of the first conductive layer. The semiconductor device also comprises a second heat conductive layer over and coupling the first via and the second via. In use, the semiconductor device generates heat, and the heat dissipates, at least partially, from the source region through the first heat conductive layer to the guard ring and the substrate.

Abstract translation: 半导体器件包括衬底，衬底上的源极区域和衬底上的保护环。 保护环与源区域隔开第一个间隔。 半导体器件还包括形成在源区和保护环上的第一导热层。 半导体器件还包括在第一导热层的第一部分上的第一通孔。 半导体器件还包括在第一导电层的第二部分上与第一通孔分离的第二通孔。 半导体器件还包括第二导热层，并且连接第一通孔和第二通孔。 在使用中，半导体器件产生热量，并且热量至少部分地从源极区域经由第一导热层消散到保护环和衬底。

公开(公告)号：US09281363B2

公开(公告)日：2016-03-08

申请号：US14681523

申请日：2015-04-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chung-Hui Chen

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L21/823487 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor structure includes a first gate-all-around (GAA) structure configured to form a first circuit and a second GAA structure configured to form a second circuit similar to the first circuit. The first GAA structure and the second GAA structure have a same of at least one of the following exemplary features: a number of GAA devices in which current flows from a first oxide definition (OD) region to a second OD region; a number of GAA devices in which current flows from the second OD region to the first OD region; a number of first OD region contact elements; a number of second OD region contact elements.

Abstract translation: 半导体结构包括构造成形成第一电路的第一栅极全能（GAA）结构和被配置为形成类似于第一电路的第二电路的第二GAA结构。 第一GAA结构和第二GAA结构具有以下示例性特征中的至少一个相同的一些GAA器件，其中电流从第一氧化物界定（OD）区域流动到第二OD区域; 许多GAA器件，其中电流从第二OD区流向第一OD区; 多个第一OD区域接触元件; 多个第二OD区域接触元件。

公开(公告)号：US08946038B2

公开(公告)日：2015-02-03

申请号：US14088538

申请日：2013-11-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hsin Hu ,  Sun-Jay Chang ,  Jaw-Juinn Horng ,  Chung-Hui Chen

IPC: H01L21/8222 ,  H01L27/06 ,  H01L29/861 ,  H01L27/08

CPC classification number: H01L27/0623 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0664 ,  H01L27/0814 ,  H01L29/861

Abstract: A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate.

Abstract translation: 在鳍状场效应晶体管（FinFET）器件中形成一个或多个二极管的方法包括形成具有鳍状图案的硬掩模层，所述鳍状图案包括隔离的鳍片区域，鳍片阵列区域和FinFET区域。 该方法还包括使用鳍状图案将多个鳍片刻蚀成半导体衬底，并在半导体衬底上沉积介电材料以填充多个鳍片之间的空间。 该方法还包括平面化半导体衬底以暴露硬掩模层。 该方法还包括将p型掺杂剂注入鳍阵列区域和FinFET区域的部分，以及将n型掺杂剂注入到隔离鳍片区域中，围绕p阱的鳍阵列区域的一部分和部分 的FinFET区域。 该方法还包括退火半导体衬底。

公开(公告)号：US12021033B2

公开(公告)日：2024-06-25

申请号：US17143354

申请日：2021-01-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chung-Hui Chen

IPC: H01L23/538 ,  H01L23/50

CPC classification number: H01L23/5384 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/5386

Abstract: An integrated circuit (IC) device includes a substrate, a first active region, first and second conductive patterns, and a first through via structure. The substrate has opposite first and second sides. The first active region is over the first side of the substrate. The first conductive pattern is over and electrically coupled to the first active region. The first through via structure extends from the second side, through the substrate, to the first side in electrical contact with the first active region. The second conductive pattern is under the second side of the substrate and electrically coupled to the first through via structure.

公开(公告)号：US20220278099A1

公开(公告)日：2022-09-01

申请号：US17542014

申请日：2021-12-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hui Chen ,  Tzu-Ching Chang ,  Weichih Chen ,  Wan-Te Chen ,  Tsung-Hsin Yu ,  Cheng-Hsiang Hsieh

IPC: H01L27/092 ,  G06F30/392 ,  G06F30/36 ,  G06F30/327

Abstract: An integrated circuit (IC) including a plurality of finfet cells designed with digital circuit design rules to provide smaller finfet cells with decreased cell heights, and analog circuit cell structures including first finfet cells of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells with decreased cell heights provide a first shorter metal track in one direction and the at least one cut metal layer provides a second shorter metal track in another direction to increase maximum electromigration currents in the integrated circuit.

公开(公告)号：US11106835B2

公开(公告)日：2021-08-31

申请号：US16518596

申请日：2019-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chung-Hui Chen

IPC: G06F30/00 ,  G06F30/394 ,  H01L21/033 ,  H01L21/311 ,  H01L23/528 ,  H01L21/768 ,  H01L27/118 ,  H01L27/02

Abstract: A method of manufacturing conductive lines in a circuit is disclosed. The method includes grouping signal traces into a first set of signal traces and a second set of signal traces, fabricating, using a first mask, at least a first conductive line of a first signal trace of the first set of signal traces, and fabricating, using a second mask, at least a second conductive line of a second signal trace of the second set of signal traces. Each signal trace of the first set of signal traces has a first width. Each signal trace of the second set of signal traces has a second width different from the first width. The grouping is based on at least a current of at least a signal trace of the signal traces.

公开(公告)号：US10444081B2

公开(公告)日：2019-10-15

申请号：US15639318

申请日：2017-06-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jaw-Juinn Horng ,  Szu-Lin Liu ,  Chung-Hui Chen

IPC: G01K3/00 ,  G01K3/04 ,  G01K7/01

Abstract: A circuit includes a first current source that provides a current and a resistive branch in series with the first current source that provides a first voltage value and a second voltage value. A capacitive device is coupled with a voltage node having a voltage value, and a switching network alternates between charging the capacitive device to have the voltage value increase to the first voltage value, and discharging the capacitive device to have the voltage value decrease to the second voltage value.

公开(公告)号：US10296032B2

公开(公告)日：2019-05-21

申请号：US15454684

申请日：2017-03-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jaw-Juinn Horng ,  Kuo-Feng Yu ,  Chung-Hui Chen

IPC: G05F3/16 ,  G05F3/30

Abstract: A bandgap reference circuit includes a first bipolar junction transistor (BJT) in series with a first current generator, the first BJT and the first current generator configured to produce a first proportional to absolute temperature (PTAT) signal. The circuit also includes a second BJT in series with a second current generator, the second BJT and the second current generator configured to produce a second PTAT signal. The bandgap reference circuit maintains a current through at least one of the first BJT or the second BJT within a constant ideality factor region of the at least one of the first BJT or the second BJT.

公开(公告)号：US20190006458A1

公开(公告)日：2019-01-03

申请号：US15966406

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hao-Chieh Chan ,  Chung-Hui Chen

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L27/08 ,  H01L21/762

Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

公开(公告)号：US09702763B2

公开(公告)日：2017-07-11

申请号：US13919274

申请日：2013-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jaw-Juinn Horng ,  Szu-Lin Liu ,  Chung-Hui Chen

IPC: G01K3/04 ,  G01K7/01

CPC classification number: G01K3/04 ,  G01K7/01 ,  Y10T307/858

Abstract: A circuit includes a comparator unit and a switching network. The comparator unit is configured to receive a first voltage value, a second voltage value and a third voltage value of a voltage node, and to provide a control signal. The switching network includes the voltage node and is configured to operate in a first condition or in a second condition based on the control signal. Based on the first condition, the voltage node is configured to have a voltage value increase to the first voltage value. Based on a second condition, the voltage node is configured to have a voltage decrease to the second voltage.