公开(公告)号：US10825532B2

公开(公告)日：2020-11-03

申请号：US16845387

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Bo Shim ,  Sang-Wan Nam ,  Ji-Ho Cho

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04 ,  G11C7/10 ,  G11C8/14

Abstract: A method of operating a memory device includes performing a data read operation on at least one victim sub-block within a memory block containing a plurality of sub-blocks therein, in response to an erase command directed to a selected sub-block within the plurality of sub-blocks. Next, a soft program operation is performed on the at least one victim sub-block. This soft programming operation is then followed by an operation to erase the selected sub-block within the plurality of sub-blocks. This operation to erase the selected sub-block may include providing an erase voltage to a bulk region of a substrate on which the memory block extends, and the at least one victim sub-block may be disposed between the selected sub-block and the substrate.

公开(公告)号：US10224105B2

公开(公告)日：2019-03-05

申请号：US15978230

申请日：2018-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Kitae Park

IPC: G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  G11C16/08 ,  G11C16/10

Abstract: A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.

公开(公告)号：US10192620B2

公开(公告)日：2019-01-29

申请号：US15816903

申请日：2017-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wandong Kim ,  Sang-Soo Park ,  Se Hwan Park ,  Sang-Wan Nam

IPC: G11C16/04 ,  G11C16/08

Abstract: A nonvolatile memory device performs a method which includes: causing a ready/busy signal pin of the nonvolatile memory device to indicate that the nonvolatile memory device is in a precharge busy state wherein the nonvolatile memory device is not available to perform memory access operations for its nonvolatile memory cells; applying one or more word line precharge voltages to one or more selected word lines among a plurality of word lines of the nonvolatile memory device to precharge the selected word lines; and, after at least a portion of the precharge operation, causing the ready/busy signal pin to transition from indicating the precharge busy state, to indicating that the nonvolatile memory device is in a ready state wherein the nonvolatile memory device is available to perform memory access operations for its nonvolatile memory cells.

公开(公告)号：US09947416B2

公开(公告)日：2018-04-17

申请号：US14811380

申请日：2015-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chi Weon Yoon ,  Donghyuk Chae ,  Jae-Woo Park ,  Sang-Wan Nam

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/06 ,  G11C16/16 ,  H01L29/792

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/16 ,  H01L29/792

Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

公开(公告)号：US09799404B2

公开(公告)日：2017-10-24

申请号：US15357291

申请日：2016-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Doo-Hyun Kim ,  Dae-Seok Byeon ,  Chi-Weon Yoon

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/06 ,  G11C16/34 ,  G11C16/10 ,  H01L27/11582 ,  G11C16/12

CPC classification number: G06F3/0619 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0655 ,  G06F3/0688 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3459 ,  H01L27/11582

Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

公开(公告)号：US09786372B2

公开(公告)日：2017-10-10

申请号：US15172929

申请日：2016-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wan Nam ,  Sun-Min Yun ,  Bongsoon Lim ,  Yoon-Hee Choi

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/04 ,  G11C16/28 ,  G11C8/08 ,  G11C16/34

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/3459

Abstract: According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a voltage generation circuit, and control logic. The memory cell array includes a plurality of memory blocks on a substrate. Each of the memory blocks includes a plurality of strings connected between bit lines and a common source line. The address decoder is configured to measure impedance information of word lines of a selected memory block. The voltage generation circuit is configured to generate word line voltages to be applied to word lines, and at least one of the word line voltages includes an offset voltage and a target voltage. The control logic is configured to adjust a level of the offset voltage and the offset time depending on the measured impedance information of the word lines.

公开(公告)号：US09704590B2

公开(公告)日：2017-07-11

申请号：US15259765

申请日：2016-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Kang-Bin Lee ,  Junghoon Park

IPC: G01C11/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/12 ,  G11C16/16

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3459 ,  H01L27/1157 ,  H01L27/11582

Abstract: An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transistors of the plurality of cell strings; adjusting voltages to be supplied to the string selection transistors according to the detected threshold voltages; and applying the adjusted voltages to the string selection transistors to select or unselect the plurality of cell strings during a programming operation.

公开(公告)号：US09659660B2

公开(公告)日：2017-05-23

申请号：US15174183

申请日：2016-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wan Nam ,  Kuihan Ko ,  Yang-Lo Ahn ,  Kitae Park

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/34 ,  G11C7/04

CPC classification number: G11C16/10 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3427

Abstract: A driving method of a nonvolatile memory device includes receiving a program command and an address. The method includes changing a number of adjacent zones of a plurality of zones formed of unselected word lines according to a location of a selected word line corresponding to the received address. The method further includes applying different zone voltages to the number of adjacent zones and remaining zones. The nonvolatile memory device includes a plurality of strings formed to penetrate word lines stacked on a substrate in a plate shape.

公开(公告)号：US09601209B2

公开(公告)日：2017-03-21

申请号：US14716550

申请日：2015-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hyun Kim ,  Young-Sun Min ,  Sung-Whan Seo ,  Won-Tae Kim ,  Sang-Wan Nam

IPC: G11C29/02 ,  G11C7/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/30 ,  G11C5/14 ,  H02M3/15 ,  H02M3/158

CPC classification number: G11C16/26 ,  G11C5/147 ,  G11C7/04 ,  G11C16/30 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  H02M3/158

Abstract: A voltage generator includes a first trim unit and a second trim unit. The first trim unit generates a first voltage variable depending on temperature variation and a second voltage invariable irrespective of the temperature variation based on a power supply voltage, and performs a first trim operation by changing a level of the second voltage. The level of the second voltage at a first temperature becomes substantially the same as a level of the first voltage at the first temperature based on the first trim operation. The second trim unit generates an output voltage based on the power supply voltage, the first and second voltages, a reference voltage and a feedback voltage, and performs a second trim operation by adjusting variation of the output voltage depending on the temperature variation based on a result of the first trim operation.

公开(公告)号：US09514827B1

公开(公告)日：2016-12-06

申请号：US15018925

申请日：2016-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Doo-Hyun Kim ,  Dae-Seok Byeon ,  Chi-Weon Yoon

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  G11C16/26 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12

CPC classification number: G06F3/0619 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0655 ,  G06F3/0688 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3459 ,  H01L27/11582

Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

Abstract translation: 如下提供存储器件。 存储单元区域包括多个块，每个块包括多个NAND串。 控制逻辑基于相对于存储器单元区域的第一边缘的第一距离的较小距离和相对于存储器单元区域的第二边缘的第二距离，将多个块划分为多个块区域，以及 使用用于该操作的多个偏置操作参数组来控制在存储单元区域上执行的操作。 每个偏差集合与块区域之一相关联。