公开(公告)号：US20160111538A1

公开(公告)日：2016-04-21

申请号：US14969702

申请日：2015-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Roh ,  Pankwi Park ,  Dongsuk Shin ,  Chulwoong Lee ,  Naein Lee

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/161

CPC classification number: H01L29/7849 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/66553 ,  H01L29/7848

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

Abstract translation: 根据本发明构思的实施例，栅极形成在衬底上，并且第一间隔物，第二间隔物和第三间隔物依次形成在栅电极的侧壁上。 蚀刻衬底以形成凹陷区域。 在凹部形成压缩应力图形。 在第三间隔件的侧壁上形成保护隔离件。 当形成凹陷区域时，去除第二间隔物的下部以在第一和第三间隔物之间​​形成间隙区域。 保护性间隔物填充间隙区域。

公开(公告)号：US09252235B2

公开(公告)日：2016-02-02

申请号：US13957912

申请日：2013-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Roh ,  Pankwi Park ,  Dongsuk Shin ,  Chulwoong Lee ,  Naein Lee

IPC: H01L21/76 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7849 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/66553 ,  H01L29/7848

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

Abstract translation: 根据本发明构思的实施例，栅极形成在衬底上，并且第一间隔物，第二间隔物和第三间隔物依次形成在栅电极的侧壁上。 蚀刻衬底以形成凹陷区域。 在凹部形成压缩应力图形。 在第三间隔件的侧壁上形成保护隔离件。 当形成凹陷区域时，去除第二间隔物的下部，以在第一和第三间隔物之间​​形成间隙区域。 保护性间隔物填充间隙区域。

公开(公告)号：US12249606B2

公开(公告)日：2025-03-11

申请号：US18414039

申请日：2024-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Keunhwi Cho ,  Myunggil Kang ,  Seokhoon Kim ,  Dongwon Kim ,  Pankwi Park ,  Dongsuk Shin

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

公开(公告)号：US20240234541A9

公开(公告)日：2024-07-11

申请号：US18190837

申请日：2023-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Edwardnamkyu Cho ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Sumin Yu ,  Seojin Jeong

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A manufacturing method of a semiconductor device, includes forming a plurality of main gate sacrificial patterns spaced apart from each other on a stacked structure of subgate sacrificial patterns and semiconductor patterns; forming a first insulating layer between main gate sacrificial patterns; removing the main gate sacrificial patterns; removing the subgate sacrificial patterns; forming a main gate dummy pattern in a space from which the main gate sacrificial patterns are removed; forming a plurality of subgate dummy patterns in a space from which the subgate sacrificial patterns are removed; forming a recess under a space where the first insulating layer is removed; forming a source/drain pattern within the recess; forming a second insulating layer on the source/drain pattern; removing the main gate dummy pattern and the subgate dummy patterns; and forming a gate electrode in a space where the main gate dummy pattern and the subgate dummy patterns are removed.

公开(公告)号：US12027596B2

公开(公告)日：2024-07-02

申请号：US18201308

申请日：2023-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ryong Ha ,  Dongwoo Kim ,  Gyeom Kim ,  Yong Seung Kim ,  Pankwi Park ,  Seung Hun Lee

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/41758 ,  H01L29/1033 ,  H01L29/42356

Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.

公开(公告)号：US20240096945A1

公开(公告)日：2024-03-21

申请号：US18527453

申请日：2023-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Seojin Jeong ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Ryong Ha

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/6656 ,  H01L29/78618

Abstract: An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.

公开(公告)号：US20240030286A1

公开(公告)日：2024-01-25

申请号：US18140905

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Heo ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Sumin Yu ,  Seojin Jeong ,  Edward Namkyu Cho ,  Ryong Ha

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66439

Abstract: An integrated circuit device includes a plurality of fin-type active areas extending in a first horizontal direction on a substrate, a plurality of channel regions respectively on the plurality of fin-type active areas, a plurality of gate lines surrounding the plurality of channel regions on the plurality of fin-type active areas and extending in a second horizontal direction that crosses the first horizontal direction, and a plurality of source/drain regions respectively at positions adjacent to the plurality of gate lines on the plurality of fin-type active areas and respectively in contact with the plurality of channel regions, and the plurality of source/drain regions respectively include a plurality of semiconductor layers and at least one air gap located therein.

公开(公告)号：US20230402459A1

公开(公告)日：2023-12-14

申请号：US18185941

申请日：2023-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seojin Jeong ,  Jungtaek Kim ,  Moonseung Yang ,  Sumin Yu ,  Edward Namkyu Cho ,  Seokhoon Kim ,  Pankwi Park

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L29/7851 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/42392

Abstract: An integrated circuit (IC) device includes a fin-type active region, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region, a source/drain region that is adjacent to the gate line on the fin-type active region and has a sidewall facing the channel region, wherein the source/drain region includes a first buffer layer, a second buffer layer, and a main body layer, which are sequentially stacked in a direction away from the fin-type active region, each include a Si1-xGex layer (x≠0) doped with a p-type dopant, and have different Ge concentrations, and the second buffer layer conformally covers a surface of the first buffer layer that faces the main body layer. A thickness ratio of the side buffer portion to the bottom buffer portion is in a range of about 0.9 to about 1.1.

公开(公告)号：US20230378336A1

公开(公告)日：2023-11-23

申请号：US18117405

申请日：2023-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu Cho ,  Jungtaek Kim ,  Moonseung Yang ,  Sumin Yu ,  Seojin Jeong ,  Seokhoon Kim ,  Pankwi Park

IPC: H01L29/775 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/775 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/0649 ,  H01L29/41775

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction, a plurality of channel layers on the active region to be spaced apart from each other in a vertical direction, perpendicular to an upper surface of the substrate, the plurality of channel layers including silicon germanium, a gate structure intersecting the active region and the plurality of channel layers on the substrate to surround the plurality of channel layers, respectively, a source/drain region on the active region on at least one side of the gate structure, the source/drain region in contact with the plurality of channel layers, and a substrate insulating layer disposed between the source/drain region and the substrate. The source/drain region includes a first layer in contact with a side surface of the gate structure, side surfaces of the plurality of channel layers, and an upper surface of the substrate insulating layer.

公开(公告)号：US11676963B2

公开(公告)日：2023-06-13

申请号：US17584877

申请日：2022-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungryul Lee ,  Yongseung Kim ,  Jungtaek Kim ,  Pankwi Park ,  Dongchan Suh ,  Moonseung Yang ,  Seojin Jeong ,  Minhee Choi ,  Ryong Ha

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/0673 ,  H01L29/4238 ,  H01L29/785

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.