公开(公告)号：US20230402510A1

公开(公告)日：2023-12-14

申请号：US18100872

申请日：2023-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namkyu CHO ,  Jungtaek Kim ,  Moon Seung Yang ,  Sumin Yu ,  Seojin Jeong ,  Seokhoon Kim ,  Pankwi Park

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/66439

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, and a source/drain pattern on a side surface of the channel pattern, the source/drain pattern including a first section between a first level and a second level that is higher than the first level, a first variation section between the second level and a third level that is higher than the second level, and a second section between the third level and a fourth level that is higher than the third level, where a rate of change in germanium concentration in the first variation section in a first direction is greater than a rate of change in germanium concentration in each of the first section and the second section in the first direction, and a germanium concentration at each of the first level and the second level is greater than 0 at % and equal to or less than 10 at %.

公开(公告)号：US20230395662A1

公开(公告)日：2023-12-07

申请号：US18299086

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seojin Jeong ,  Jungtaek Kim ,  Moonseung Yang ,  Sumin Yu ,  Namkyu Cho ,  Seokhoon Kim ,  Pankwi Park

IPC: H01L29/08 ,  H01L29/775 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/0673

Abstract: Semiconductor device may include an active region extending in a first direction, channel layers spaced apart from each other in a vertical direction, a gate structure extending on the active region and the channel layers to surround the channel layers and extending in a second direction, and a source/drain region on the active region adjacent to a side of the gate structure and contacting the plurality of channel layers. The source/drain region includes first to sixth epitaxial layers that are sequentially stacked in the vertical direction and have respective first to sixth germanium (Ge) concentrations. The first Ge concentration is lower than the second Ge concentration, the third Ge concentration is lower than the second Ge concentration and the fourth Ge concentration, and the fifth Ge concentration is lower than the fourth Ge concentration and the sixth Ge concentration.

公开(公告)号：US20240136425A1

公开(公告)日：2024-04-25

申请号：US18190837

申请日：2023-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Edwardnamkyu Cho ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Sumin Yu ,  Seojin Jeong

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A manufacturing method of a semiconductor device, includes forming a plurality of main gate sacrificial patterns spaced apart from each other on a stacked structure of subgate sacrificial patterns and semiconductor patterns; forming a first insulating layer between main gate sacrificial patterns; removing the main gate sacrificial patterns; removing the subgate sacrificial patterns; forming a main gate dummy pattern in a space from which the main gate sacrificial patterns are removed; forming a plurality of subgate dummy patterns in a space from which the subgate sacrificial patterns are removed; forming a recess under a space where the first insulating layer is removed; forming a source/drain pattern within the recess; forming a second insulating layer on the source/drain pattern; removing the main gate dummy pattern and the subgate dummy patterns; and forming a gate electrode in a space where the main gate dummy pattern and the subgate dummy patterns are removed.

公开(公告)号：US11888026B2

公开(公告)日：2024-01-30

申请号：US17467944

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Seojin Jeong ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Ryong Ha

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/6656 ,  H01L29/78618

Abstract: An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.

公开(公告)号：US20240105776A1

公开(公告)日：2024-03-28

申请号：US18229349

申请日：2023-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu Cho ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Seojin Jeong

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02658 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes a substrate including an active region extending in a first direction, a gate structure intersecting the active region on the substrate and extending in a second direction, where the active region includes a recessed region at at least one side of the gate structure, a plurality of channel layers on the active region, spaced apart from each other in a third direction that is substantially perpendicular to an upper surface of the substrate, and at least partially surrounded by the gate structure and a source/drain region in the recessed region of the active region and connected to the plurality of channel layers.

公开(公告)号：US20220190109A1

公开(公告)日：2022-06-16

申请号：US17467944

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Seojin Jeong ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Ryong Ha

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

Abstract: An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.

公开(公告)号：US11264381B2

公开(公告)日：2022-03-01

申请号：US16841806

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungryul Lee ,  Yongseung Kim ,  Jungtaek Kim ,  Pankwi Park ,  Dongchan Suh ,  Moonseung Yang ,  Seojin Jeong ,  Minhee Choi ,  Ryong Ha

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.

公开(公告)号：US11145723B2

公开(公告)日：2021-10-12

申请号：US16720363

申请日：2019-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seojin Jeong ,  Jinyeong Joe ,  Seokhoon Kim ,  Jeongho Yoo ,  Seung Hun Lee ,  Sihyung Lee

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/04 ,  H01L29/167 ,  H01L29/36 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02

Abstract: A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

公开(公告)号：US20240234541A9

公开(公告)日：2024-07-11

申请号：US18190837

申请日：2023-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Edwardnamkyu Cho ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Sumin Yu ,  Seojin Jeong

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A manufacturing method of a semiconductor device, includes forming a plurality of main gate sacrificial patterns spaced apart from each other on a stacked structure of subgate sacrificial patterns and semiconductor patterns; forming a first insulating layer between main gate sacrificial patterns; removing the main gate sacrificial patterns; removing the subgate sacrificial patterns; forming a main gate dummy pattern in a space from which the main gate sacrificial patterns are removed; forming a plurality of subgate dummy patterns in a space from which the subgate sacrificial patterns are removed; forming a recess under a space where the first insulating layer is removed; forming a source/drain pattern within the recess; forming a second insulating layer on the source/drain pattern; removing the main gate dummy pattern and the subgate dummy patterns; and forming a gate electrode in a space where the main gate dummy pattern and the subgate dummy patterns are removed.

公开(公告)号：US20240096945A1

公开(公告)日：2024-03-21

申请号：US18527453

申请日：2023-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Seojin Jeong ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Ryong Ha

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/6656 ,  H01L29/78618

Abstract: An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.