公开(公告)号：US11888026B2

公开(公告)日：2024-01-30

申请号：US17467944

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Seojin Jeong ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Ryong Ha

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/6656 ,  H01L29/78618

Abstract: An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.

公开(公告)号：US11948942B2

公开(公告)日：2024-04-02

申请号：US18122253

申请日：2023-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Choi ,  Keunhwi Cho ,  Myunggil Kang ,  Seokhoon Kim ,  Dongwon Kim ,  Pankwi Park ,  Dongsuk Shin

IPC: H01L29/08 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/167 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1−xGex layer, where x≠0, and the inner blocking layer including a Si layer.

公开(公告)号：US20220190109A1

公开(公告)日：2022-06-16

申请号：US17467944

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Seojin Jeong ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Ryong Ha

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

Abstract: An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.

公开(公告)号：US11264381B2

公开(公告)日：2022-03-01

申请号：US16841806

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungryul Lee ,  Yongseung Kim ,  Jungtaek Kim ,  Pankwi Park ,  Dongchan Suh ,  Moonseung Yang ,  Seojin Jeong ,  Minhee Choi ,  Ryong Ha

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.

公开(公告)号：US12249606B2

公开(公告)日：2025-03-11

申请号：US18414039

申请日：2024-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Keunhwi Cho ,  Myunggil Kang ,  Seokhoon Kim ,  Dongwon Kim ,  Pankwi Park ,  Dongsuk Shin

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

公开(公告)号：US20240096945A1

公开(公告)日：2024-03-21

申请号：US18527453

申请日：2023-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Seojin Jeong ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Ryong Ha

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/6656 ,  H01L29/78618

Abstract: An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.

公开(公告)号：US11676963B2

公开(公告)日：2023-06-13

申请号：US17584877

申请日：2022-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungryul Lee ,  Yongseung Kim ,  Jungtaek Kim ,  Pankwi Park ,  Dongchan Suh ,  Moonseung Yang ,  Seojin Jeong ,  Minhee Choi ,  Ryong Ha

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/0673 ,  H01L29/4238 ,  H01L29/785

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.

公开(公告)号：US11631674B2

公开(公告)日：2023-04-18

申请号：US17231114

申请日：2021-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Choi ,  Keunhwi Cho ,  Myunggil Kang ,  Seokhoon Kim ,  Dongwon Kim ,  Pankwi Park ,  Dongsuk Shin

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.