公开(公告)号：US10205025B2

公开(公告)日：2019-02-12

申请号：US15276779

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: Methods to achieve strained channel finFET devices and resulting finFET devices are presented. In an embodiment, a method for processing a field effect transistor (FET) device may include forming a fin structure comprising a fin channel on a substrate. The method may also include forming a sacrificial epitaxial layer on a side of the fin structure. Additionally, the method may include forming a deep recess in a region that includes at least a portion of the fin structure, wherein the fin structure and sacrificial layer relax to form a strain on the fin channel. The method may also include depositing source/drain (SD) material in the deep recess to preserve the strain on the fin channel.

公开(公告)号：US20190012593A1

公开(公告)日：2019-01-10

申请号：US15806259

申请日：2017-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/78 ,  H01L29/423

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US10026652B2

公开(公告)日：2018-07-17

申请号：US15343157

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

Abstract: Multi-Vt horizontal nanosheet devices and a method of making the same. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (hNS devices) on a top surface of a substrate, the plurality of hNS devices including a first hNS device and a second hNS device spaced apart from each other horizontally. Each of the hNS devices includes a first and a second horizontal nanosheets spaced apart vertically; and a gate stack between the first and second horizontal nanosheets, the gate stack including a work function metal (WFM) layer. A thickness of the first and second horizontal nanosheets of the first hNS device is different from a thickness of the first and second horizontal nanosheets of the second hNS device, and a thickness of the WFM layer of the first hNS device is different from a thickness of the WFM layer of the second hNS device.

公开(公告)号：US10008580B2

公开(公告)日：2018-06-26

申请号：US15346535

申请日：2016-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66522 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66856 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: According to an embodiment of the present invention, a method of manufacturing a FET device having a set BTBT leakage and a maximum VDD includes: determining an x value in InxGa1-xAs according to the BTBT leakage and the maximum VDD, and forming a channel utilizing InxGa1-xA, wherein x is not 0.53.

公开(公告)号：US20180053859A1

公开(公告)日：2018-02-22

申请号：US15359480

申请日：2016-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Robert M. Wallace ,  Xiaoye Qin

IPC: H01L29/786 ,  H01L29/04 ,  H01L21/02

CPC classification number: H01L29/78681 ,  H01L21/02172 ,  H01L21/02293 ,  H01L29/04 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

公开(公告)号：US09711414B2

公开(公告)日：2017-07-18

申请号：US14887484

申请日：2015-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Robert C. Bowen ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/823828 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/22 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/775 ,  H01L29/7847

Abstract: Exemplary embodiments provide for fabricating a biaxially strained nanosheet. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial superlattice having one or more periods, each of the periods comprising at least three layers, an active material layer, a first sacrificial material layer and a second sacrificial material layer, the first and second sacrificial material layers having different material properties; in each of the one or more periods, placing each of the active material layers between the first and second sacrificial material layers, wherein lattice constants of the first and second sacrificial material layers are different than the active material layer and impose biaxial stress in the active material layer; selectively etching away all of the first sacrificial material layers thereby exposing one surface of the active material for additional processing, while the biaxial strain in the active material layers is maintained by the second sacrificial material layers; and selectively etching away all of the second sacrificial material layers thereby exposing a second surface of the active material layers for additional processing.

公开(公告)号：US09698234B2

公开(公告)日：2017-07-04

申请号：US14666770

申请日：2015-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Mark S. Rodder ,  Wei-E Wang

IPC: H01L21/31 ,  H01L31/113 ,  H01L29/51 ,  H01L21/28 ,  H01L29/778

CPC classification number: H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/778

Abstract: Exemplary embodiments provide for fabricating a field effect transistor (FET) with an interface layer for a gate stack using an O3 post treatment. Aspects of the exemplary embodiments include: forming a semiconductor body upon a substrate; cleaning the surface of the semiconductor body; depositing a first dielectric layer on the semiconductor body; performing an O3 treatment to form a new interface layer that incorporates material from the substrate and material from the first dielectric layer; and performing gate stack processing, including deposition of a gate electrode.

公开(公告)号：US09601586B1

公开(公告)日：2017-03-21

申请号：US15017352

申请日：2016-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Mark S. Rodder

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/66 ,  H01L29/45 ,  H01L21/8234 ,  H01L29/08

CPC classification number: H01L29/41791 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66545

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device includes forming a metal layer on source/drain regions of respective semiconductor structures, after replacing a dummy gate structure of the semiconductor device with a metal gate structure. The method includes forming a contact structure that overlaps the metal layer on one or more, but not all, of the semiconductor structures. Moreover, an insulating material is between the source/drain regions.

公开(公告)号：US09425275B2

公开(公告)日：2016-08-23

申请号：US14728104

申请日：2015-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Dharmendar Reddy Palle ,  Borna J. Obradovic

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L29/4238 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/0886

Abstract: An integrated circuit chip includes a semiconductor substrate, a first back-end-of-line unit circuit that includes a first group of field effect transistors, a second gate-loaded unit circuit that includes a second group of field effect transistors. The first group of field effect transistors includes a first transistor and the second group of field effect transistors includes a second transistor. A bottom surface of a gate electrode of the first transistor extends closer to a bottom surface of the semiconductor substrate than does a bottom surface of a gate electrode of the second transistor.

Abstract translation: 集成电路芯片包括半导体衬底，第一后端线单元电路，其包括第一组场效应晶体管，第二栅极负载单元电路，其包括第二组场效应晶体管。 第一组场效应晶体管包括第一晶体管，第二组场效应晶体管包括第二晶体管。 与第二晶体管的栅电极的底表面相比，第一晶体管的栅电极的底表面比半导体衬底的底表面更靠近。

公开(公告)号：US09257327B2

公开(公告)日：2016-02-09

申请号：US13859482

申请日：2013-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Kang-ill Seo

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/092

CPC classification number: H01L21/76243 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/78609

Abstract: Methods of forming a Field Effect Transistor (FET) are provided. The methods may include forming a region that provides enhanced oxidation under a fin-shaped FET (FinFET) body.

Abstract translation: 提供了形成场效应晶体管（FET）的方法。 所述方法可以包括形成在鳍状FET（FinFET）体下提供增强氧化的区域。