公开(公告)号：US10593700B2

公开(公告)日：2020-03-17

申请号：US15855996

申请日：2017-12-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul Gupta ,  Xiangdong Chen ,  Ohsang Kwon ,  Foua Vang ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L27/118 ,  H01L23/535 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.

公开(公告)号：US20200058792A1

公开(公告)日：2020-02-20

申请号：US16104522

申请日：2018-08-17

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  Peijie Feng

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

公开(公告)号：US10439039B2

公开(公告)日：2019-10-08

申请号：US15081702

申请日：2016-03-25

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H01L29/161 ,  H01L29/423 ,  H01L29/786

Abstract: An integrated circuit includes a FinFET and a nanostructure FET. The integrated circuit includes a bulk substrate. The integrated circuit also includes a fin field effect transistor (FinFET) coupled to the bulk substrate. The FinFET includes a first source region, a first drain region, and a fin extending between the first source region and the first drain region. The integrated circuit also includes a nanostructure FET coupled to the bulk substrate. The nanostructure FET includes a second source region, a second drain region, and a stack of at least two nanostructures extending between the second source region and the second drain region.

公开(公告)号：US20190296126A1

公开(公告)日：2019-09-26

申请号：US15927343

申请日：2018-03-21

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  John Jianhong Zhu

IPC: H01L29/66 ,  H01L29/06 ,  H01L23/535 ,  H01L27/088 ,  H01L27/02 ,  H01L21/768 ,  H01L29/417

Abstract: Systems and methods for dummy gate tie-offs in a self-aligned gate contact (SAGC) cell are disclosed. In particular, exemplary aspects contemplate a two-part etching process to remove hardmasks formed from different materials from adjacent elements. A metal fill material may then be used to tie off the adjacent elements. The use of the two-part etching process allows SAGC techniques to be used for a first portion of a cell while still providing a technique to allow a tie-off in a second portion of the cell. The tie-off may be used with a dummy gate to provide isolation between cells.

公开(公告)号：US10332881B1

公开(公告)日：2019-06-25

申请号：US16104544

申请日：2018-08-17

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Kern Rim

IPC: H01L21/02 ,  H01L27/02 ,  H01L27/11 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: Integrating a gate-all-around (GAA) field-effect transistor(s) and a FinFET(s) on a common substrate of a semiconductor die is disclosed. GAA FETs and FinFETs can form integrated circuits (ICs). GAA FETs and FinFETs are integrated on a common substrate to optimize advantages of each type of FET. For example, FinFETs may be formed in the common substrate in the semiconductor die for forming circuits where reduced resistance and capacitance are important for performance, whereas GAA FETs may be formed in the common substrate in the semiconductor die for forming circuits with decreased threshold voltage to allow voltage scaling to lower supply voltages to reduce power consumption and also to reduce silicon area as a result of vertically stacked devices. This supports a designer having the freedom to separate control the channel width of the GAA FETs and FinFETs, which may be important for controlling drive strength and/or area for different circuits.

公开(公告)号：US10163792B2

公开(公告)日：2018-12-25

申请号：US14444104

申请日：2014-07-28

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Choh Fei Yeap ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L23/522 ,  H01L23/532

Abstract: An apparatus includes a first interconnect and a first barrier structure. The first barrier structure is in contact with a dielectric material. The apparatus further includes a first protective structure in contact with the first barrier structure and an etch stop layer. An airgap is defined at least in part by the first protective structure and the etch stop layer.

公开(公告)号：US09984029B2

公开(公告)日：2018-05-29

申请号：US14484137

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Kern Rim ,  Stanley Seungchul Song ,  Xiangdong Chen ,  Raymond George Stephany ,  John Jianhong Zhu ,  Ohsang Kwon ,  Esin Terzioglu ,  Choh Fei Yeap

IPC: H01L23/528 ,  G06F13/40 ,  G06F13/42 ,  G06F17/50 ,  H01L27/02

CPC classification number: G06F13/4068 ,  G06F13/4221 ,  G06F17/5068 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.

公开(公告)号：US09887209B2

公开(公告)日：2018-02-06

申请号：US14279250

申请日：2014-05-15

Applicant: QUALCOMM Incorporated

Inventor： Mukul Gupta ,  Xiangdong Chen ,  Ohsang Kwon ,  Foua Vang ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L21/44 ,  H01L27/118 ,  H01L23/535 ,  H01L27/092 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only.

公开(公告)号：US09871121B2

公开(公告)日：2018-01-16

申请号：US14341568

申请日：2014-07-25

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Da Yang ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/6681 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

公开(公告)号：US20170338215A1

公开(公告)日：2017-11-23

申请号：US15160992

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Giridhar Nallapati ,  Da Yang ,  Kern Rim ,  Robert Bucki ,  Choh Fei Yeap

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/11803 ,  H01L28/00 ,  H01L2027/11809 ,  H01L2027/11824 ,  H01L2027/11874 ,  H01L2027/11881

Abstract: A heterogeneous cell array includes a first column of cells and a second column of cells. The first column of cells includes a first cell having a first area and a second cell having the first area. The first cell includes two fin-type field effect transistors having a first number of fins and the second cell includes two fin-type field effect transistors having the first number of fins. The second column of cells includes a third cell having a second area. The third cell is adjacent to the first cell and to the second cell, and the third cell includes two fin-type field effect transistors having a second number of fins. The second area is greater than the first area, and the second number of fins is greater than the first number of fins.