公开(公告)号：US20190189457A1

公开(公告)日：2019-06-20

申请号：US15842841

申请日：2017-12-14

Applicant: International Business Machines Corporation

Inventor： Fee Li Lie ,  Dongbing Shao ,  Robert Wong ,  Yongan Xu

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3065

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

公开(公告)号：US20190080958A1

公开(公告)日：2019-03-14

申请号：US15703097

申请日：2017-09-13

Applicant: International Business Machines Corporation

Inventor： Cheng Chi ,  Kafai Lai ,  Chi-Chun Liu ,  Yongan Xu

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76816 ,  H01L21/02118 ,  H01L21/02356 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76897

Abstract: A method of forming an interconnect element includes forming a trench in a dielectric material. The trench has a width equal to twice a natural pitch of a block copolymer. The block copolymer includes a first polymer and a second polymer. The method includes filling the trench with the block copolymer.

公开(公告)号：US10157789B2

公开(公告)日：2018-12-18

申请号：US15239178

申请日：2016-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

公开(公告)号：US10147803B2

公开(公告)日：2018-12-04

申请号：US15214851

申请日：2016-07-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Junli Wang ,  Yongan Xu ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/08 ,  H01L29/49 ,  H01L29/40

Abstract: A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.

公开(公告)号：US20160336225A1

公开(公告)日：2016-11-17

申请号：US14710894

申请日：2015-05-13

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Abstract translation: 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。

公开(公告)号：US20160300721A1

公开(公告)日：2016-10-13

申请号：US15182995

申请日：2016-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Junli Wang ,  Yongan Xu ,  Yunpeng Yin

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/28088 ,  H01L21/31122 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.

公开(公告)号：US09330965B2

公开(公告)日：2016-05-03

申请号：US14837827

申请日：2015-08-27

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Yunpeng Yin ,  Ailian Zhao

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/76898

Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.

公开(公告)号：US09219007B2

公开(公告)日：2015-12-22

申请号：US13913823

申请日：2013-06-10

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC.

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Yunpeng Yin ,  Ailian Zhao

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/76898

Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.

Abstract translation: 一种包括在衬底上形成五层硬掩模的方法，所述五层硬掩模包括在第二硬掩模层上方的第一硬掩模层; 在第一硬掩模层中形成沟槽图案; 将第一通孔条图案从五层硬掩模上方的第一光致抗蚀剂层转移到第二硬掩模层中，产生第一通孔图案，第二硬掩模层中的第一通孔图案与沟槽图案重叠并且在 双面通过第一个硬掩模层中的沟槽图案; 以及将所述第一通孔图案从所述第二硬掩模层转移到所述衬底中，从而产生自对准的通孔，所述自对准通孔开口通过所述第二硬掩模层中的所述第一通孔图案在所有侧面上自对准。

公开(公告)号：US20140199615A1

公开(公告)日：2014-07-17

申请号：US13741579

申请日：2013-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Martin Burkhardt ,  Yongan Xu

IPC: G03F1/00

CPC classification number: G03F1/144 ,  G03F1/36

Abstract: A two-dimensional dense array of contact holes can be printed on a negative photoresist employing a combination of a quadrupole illumination lens and a lithographic mask including a criss-cross pattern of opaque lines. The openings in the quadrupole illumination lens are aligned along the perpendicular directions of the opaque lines. Discrete contact holes can be printed on a negative photoresist employing a combination of a quadrupole illumination lens and a lithographic mask including a criss-cross pattern of opaque subresolution assist features and discrete opaque cross patterns. Alternately, a two-dimensional array of contact holes can be printed on a negative photoresist employing a quadrupole illumination lens and a checkerboard pattern of openings. The openings in the quadrupole illumination lens are in diagonal directions.

Abstract translation: 接触孔的二维密集阵列可以使用四极照明透镜和包括不透明线的十字交叉图案的光刻掩模的组合在印刷电路板上印刷。 四极照明透镜中的开口沿着不透明线的垂直方向排列。 分离接触孔可以使用四极照明透镜和包括不透明分解辅助特征和离散不透明交叉图案的十字交叉图案的光刻掩模的组合来印刷在负光致抗蚀剂上。 或者，二维阵列的接触孔可以使用四极照明透镜和棋盘图案的开口印刷在负光致抗蚀剂上。 四极照明透镜中的开口处于对角线方向。

公开(公告)号：US12094774B2

公开(公告)日：2024-09-17

申请号：US17474292

申请日：2021-09-14

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Yongan Xu ,  Hsueh-Chung Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76885 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5283

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures having a back-end-of-line (BEOL) single damascene (SD) top via spacer defined by pillar mandrels. In a non-limiting embodiment of the invention, a first conductive line is formed in a first dielectric layer. A mandrel is formed over the first conductive line and a spacer is formed on a sidewall of the mandrel. A portion of a second dielectric layer is recessed to expose a top surface of the spacer and a top surface of the mandrel and the mandrel is removed. The spacer prevents damage to the second dielectric layer while removing the mandrel. The mandrel is replaced with a conductive material. A first portion of the conductive material defines a via and a second portion of the conductive material defines a second conductive line. The via couples the first conductive line to the second conductive line.