公开(公告)号：US20150380356A1

公开(公告)日：2015-12-31

申请号：US14844515

申请日：2015-09-03

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L23/538 ,  H01L23/528 ,  H05K1/18 ,  H01L23/367 ,  H01L23/373 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5389 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/433 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/2518 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0266 ,  H05K1/185 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

Abstract translation: 封装结构包括介电层，至少一个连接到电介质层的半导体器件，一个或多个施加到电介质层的电介质片和半导体器件，以将半导体器件嵌入其中，并且多个 形成在形成在电介质层和一个或多个电介质层中的至少一个中的半导体器件上的通孔。 封装结构还包括形成在通孔中的金属互连和在封装结构的一个或多个向外表面上以形成与半导体器件的电互连的金属互连。 电介质层由在层压过程中不流动的材料组成，并且所述一个或多个电介质片中的每一个由可固化材料构成，所述可固化材料构造成在层压过程中固化时熔化和流动，以便填充任何空气 半导体器件周围的间隙。

公开(公告)号：US20150194375A1

公开(公告)日：2015-07-09

申请号：US14665735

申请日：2015-03-23

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49579 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

Abstract translation: 功率覆盖（POL）结构包括POL子模块。 POL子模块包括电介质层和具有附着到电介质层的顶表面的半导体器件。 半导体器件的顶表面具有形成在其上的至少一个接触焊盘。 POL子模块还包括金属互连结构，其延伸穿过介电层并且电耦合到半导体器件的至少一个接触焊盘。 导电垫片耦合到半导体器件的底表面，并且热界面的第一侧耦合到导电垫片。 散热器耦合到电绝缘热接口的第二侧。

公开(公告)号：US08987876B2

公开(公告)日：2015-03-24

申请号：US13897638

申请日：2013-05-20

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495 ,  H01L23/433 ,  H01L23/538 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/49575 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49579 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

Abstract translation: 功率覆盖（POL）结构包括POL子模块。 POL子模块包括电介质层和具有附着到电介质层的顶表面的半导体器件。 半导体器件的顶表面具有形成在其上的至少一个接触焊盘。 POL子模块还包括金属互连结构，其延伸穿过介电层并且电耦合到半导体器件的至少一个接触焊盘。 导电垫片耦合到半导体器件的底表面，并且热界面的第一侧耦合到导电垫片。 散热器耦合到电绝缘热接口的第二侧。

公开(公告)号：US20140264799A1

公开(公告)日：2014-09-18

申请号：US13897638

申请日：2013-05-20

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Shakti Singh Chauhan

IPC: H01L23/495 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49579 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

Abstract translation: 功率覆盖（POL）结构包括POL子模块。 POL子模块包括电介质层和具有附着到电介质层的顶表面的半导体器件。 半导体器件的顶表面具有形成在其上的至少一个接触焊盘。 POL子模块还包括金属互连结构，其延伸穿过介电层并且电耦合到半导体器件的至少一个接触焊盘。 导电垫片耦合到半导体器件的底表面，并且热界面的第一侧耦合到导电垫片。 散热器耦合到电绝缘热接口的第二侧。

公开(公告)号：US08829690B2

公开(公告)日：2014-09-09

申请号：US14138333

申请日：2013-12-23

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Kevin Matthew Durocher ,  Scott Smith ,  Laura A. Principe

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/5226 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/92 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/17151 ,  H01L2924/19105 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.

Abstract translation: 公开了一种用于芯片封装制造的系统和方法。 芯片封装包括其中形成有开口的基底再分布层，具有形成在其中的没有粘合材料的窗口的粘合剂层和通过粘合剂层固定到基底再分布层的模具，模具是 与窗口对齐，使得只有模具的周边接触粘合剂层。 屏蔽元件位于基底再分布层和粘合剂层之间，该粘合剂层通常与形成在基底再分布层中的开口和粘合剂层的窗口对齐，使得仅屏蔽元件的周边附着到 粘合剂层。 屏蔽元件通过气隙与模具分离，并且被配置为可选择性地从粘合剂层移除以暴露模具的前表面。

公开(公告)号：US10204881B2

公开(公告)日：2019-02-12

申请号：US15472912

申请日：2017-03-29

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/78 ,  H01L25/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/528 ,  H01L25/07 ,  H01L23/31 ,  H01L23/525

Abstract: A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.

公开(公告)号：US09953917B1

公开(公告)日：2018-04-24

申请号：US15375826

申请日：2016-12-12

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Raymond Albert Fillion ,  Paul Alan McConnelee

IPC: H01L25/00 ,  H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5228 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/18

Abstract: An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a pass-through structure coupled to the first side of the insulating substrate. The pass-through structure includes an insulating core, a resistor disposed proximate a top surface of the insulating core, and at least one through-hole structure forming at least one conductive pathway through a thickness of the insulating core. A patterned metallization layer is formed on a second side of the insulating substrate. The patterned metallization layer is electrically coupled to at least one first conductive pad of the semiconductor device and electrically couples at least one second conductive pad of the semiconductor device to a through-hole structure of the at least one through-hole structure through the resistor.

公开(公告)号：US09847236B2

公开(公告)日：2017-12-19

申请号：US15594794

申请日：2017-05-15

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L29/80 ,  H01L31/112 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/83895 ,  H01L2224/83931 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00012

Abstract: An electronics package includes a lower insulating layer, an upper insulating layer coupled to the lower insulating layer, and a conductive contact pad coupled to a second surface of the upper insulating layer. An electrical component is positioned within an opening formed through the upper insulating layer. A first interconnect layer extends through at least one via in the lower insulating layer to electrically couple with at least one contact pad on the electrical component and a second interconnect layer extends through at least one via in the upper insulating layer and electrically couples the first interconnect layer to the conductive contact pad.

公开(公告)号：US20170200692A1

公开(公告)日：2017-07-13

申请号：US15472912

申请日：2017-03-29

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/78 ,  H01L25/00 ,  H01L21/768 ,  H01L21/683 ,  H01L23/528 ,  H01L25/07

CPC classification number: H01L24/46 ,  H01L21/6835 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/3164 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/85 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/03466 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/24137 ,  H01L2224/29101 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/4847 ,  H01L2224/48847 ,  H01L2224/4903 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/8203 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/1302 ,  H01L2924/13023 ,  H01L2924/13034 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.

公开(公告)号：US09184124B2

公开(公告)日：2015-11-10

申请号：US14547667

申请日：2014-11-19

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC: H01L21/70 ,  H01L23/498 ,  H01L23/31 ,  H01L23/373 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/07 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/3178 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L24/95 ,  H01L25/072 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/8384 ,  H01L2224/92144 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.