公开(公告)号：US12087854B2

公开(公告)日：2024-09-10

申请号：US17929858

申请日：2022-09-06

Applicant: Wolfspeed, Inc.

Inventor： Daniel Jenner Lichtenwalner ,  Sei-Hyung Ryu ,  Kijeong Han ,  Edward Robert Van Brunt

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/66 ,  H01L29/861 ,  H01L29/872

CPC classification number: H01L29/7806 ,  H01L21/046 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/861 ,  H01L29/872

Abstract: A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers.

公开(公告)号：US20240274710A1

公开(公告)日：2024-08-15

申请号：US18645785

申请日：2024-04-25

Applicant: Huawei Digital Power Technologies Co., Ltd

Inventor： Wentao Yang ,  Loucheng Dai ,  Huiyuan Zhang ,  Qian Zhao ,  Runtao Ning

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7806 ,  H01L21/0465 ,  H01L21/049 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/66068

Abstract: An example SiC MOSFET includes a SiC semiconductor substrate (SSS), a drift layer on the SSS having a fin-shaped channel layer (FSCL) with a source region and a first insulated isolating layer. The FSCL does not cover the first insulated isolating layer, and the FSCL and the source region are of a stacking structure, and includes a gate electrode on the first insulated isolating layer that is separately on two sides of the stacking structure, a gate oxide layer between the gate electrode and the stacking structure, a second insulated isolating layer that covers an external side wall and an upper surface of the gate electrode, and a source electrode that covers the first insulated isolating layer, the second insulated isolating layer, and the source region. The SiC MOSFET further includes a drain electrode on a side of the SSS that is separated from the drift layer.

公开(公告)号：US12062698B2

公开(公告)日：2024-08-13

申请号：US17631730

申请日：2020-07-31

Applicant: Hitachi Energy Ltd

Inventor： Marco Bellini ,  Lars Knoll ,  Stephan Wirths

IPC: H01L23/00 ,  H01L21/04 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L21/0485 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7813

Abstract: A silicon carbide transistor device includes a silicon carbide semiconductor and a silicon carbide epitaxial layer formed at a top surface of the substrate. A source structure is formed in a top surface of the silicon carbide epitaxial layer and includes a p-well region, a n-type source region and a p-type contact region. A source contact structure is formed over and electrically connected to a top surface of the source structure. A planar gate structure includes a gate dielectric and a gate runner adjacent a p-type channel region. The gate dielectric covers the channel region, at least part of the source structure and at least part of the source contact structure. The gate runner is electrically insulated from the channel region and the source structure and the source contact structure by the gate dielectric and overlaps the channel region.

公开(公告)号：US12057316B2

公开(公告)日：2024-08-06

申请号：US17476829

申请日：2021-09-16

Applicant: Infineon Technologies AG

Inventor： Moriz Jelinek ,  Paul Ellinghaus ,  Axel Koenig ,  Caspar Leendertz ,  Hans-Joachim Schulze ,  Werner Schustereder

IPC: H01L21/265 ,  H01L21/04 ,  H01L29/04 ,  H01L29/16 ,  H01L29/167

CPC classification number: H01L21/047 ,  H01L29/045 ,  H01L29/1608

Abstract: A method includes orienting a silicon carbide layer to a first crystal channel direction relative to a first ion beam and implanting phosphorous into the silicon carbide layer using the first ion beam to define a first doped region in the silicon carbide layer. A deviation angle between the first crystal channel direction and the first ion beam is less than ±1° and the first crystal channel direction comprises a direction or a direction.

公开(公告)号：US20240258424A1

公开(公告)日：2024-08-01

申请号：US18519738

申请日：2023-11-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Yoshiyuki SAKAI

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/0465 ,  H01L29/063 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

Abstract: A silicon carbide semiconductor device includes: a drift layer of a first conductivity-type including silicon carbide; a base region of a second conductivity-type provided on a top surface side of the drift layer; a main region of the first conductivity-type provided on a top surface side of the base region; a gate electrode buried inside a trench with a gate insulating film interposed; and a main electrode provided in contact with the main region, wherein the main region includes a first region with a bottom surface in contact with the base region, and a second region including a 3C structure and provided at an upper part of the first region separately from the gate insulating film inside the trench so as to be in contact with the main electrode.

公开(公告)号：US20240258375A1

公开(公告)日：2024-08-01

申请号：US18160949

申请日：2023-01-27

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Pratik B. Vyas ,  El Mehdi Bazizi ,  Stephen Weeks ,  Ludovico Megalini ,  Siddarth Krishnan

IPC: H01L29/10 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/105 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/66068

Abstract: A silicon carbide transistor may be formed with a channel that includes a p-doped region between n-doped source and drain regions. A counter-doped region may be formed at the top of the channel directly underneath the gate oxide. Instead of using the conventional doping levels for the p-doped region, the doping concentration may be increase to be greater than about 1e18 cm3. The transistor may also include pocket regions on one or both sides of the channel. The pocket regions may be formed in the counter-doped region and may extend up to the gate oxide. These improvements individually and/or in combination may increase the current in the channel of the transistor without significantly increasing the threshold voltage beyond acceptable operating limits.

公开(公告)号：US20240250138A1

公开(公告)日：2024-07-25

申请号：US18624602

申请日：2024-04-02

Applicant: ROHM CO., LTD.

Inventor： Yuki NAKANO ,  Ryota NAKAMURA ,  Katsuhisa NAGAO

IPC: H01L29/423 ,  H01L21/04 ,  H01L29/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/167 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/4236 ,  H01L21/046 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/78684

Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.

公开(公告)号：US20240249935A1

公开(公告)日：2024-07-25

申请号：US18224652

申请日：2023-07-21

Applicant: EQ TECH PLUS CO., LTD.

Inventor： Dong Hwa SHIN ,  Yong Weon KIM

IPC: H01L21/02 ,  H01L21/04 ,  H01L29/40

CPC classification number: H01L21/02236 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/049 ,  H01L29/401

Abstract: Provided is a method of forming a thin film to minimize an increase in defects at an interface during a high-temperature oxidation process of a SiC substrate. The method includes depositing a first thin film on the SiC substrate by applying a radical gas, forming an oxide film on the first thin film by performing the high-temperature oxidation process, and performing annealing on the oxide film.

公开(公告)号：US20240222492A1

公开(公告)日：2024-07-04

申请号：US18557210

申请日：2022-04-25

Applicant: Robert Bosch GmbH

Inventor： Jens Baringhaus ,  Christian Huber

IPC: H01L29/78 ,  H01L21/04 ,  H01L21/225 ,  H01L21/304 ,  H01L21/683 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/0485 ,  H01L21/2253 ,  H01L21/304 ,  H01L21/6835 ,  H01L29/66712

Abstract: A method for producing vertical power semiconductor components. The method includes: applying a first side of a silicon wafer onto a subcarrier wafer, wherein a front side of the vertical power semiconductor components is arranged on the first side of the silicon wafer and the front side of the vertical power semiconductor components comprises a buffer layer and a drift layer; grinding the silicon wafer to a specific thickness; dry etching the silicon wafer; etching the buffer layer; implanting ions into the drift layer, wherein a contact semiconductor layer is formed; generating an ohmic contact by applying a metal layer onto the contact semiconductor layer; and removing the subcarrier wafer.

公开(公告)号：US12027579B2

公开(公告)日：2024-07-02

申请号：US16480203

申请日：2018-01-25

Applicant: ROHM CO., LTD.

Inventor： Seigo Mori ,  Masatoshi Aketa

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/04 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L29/16 ,  H01L29/32 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872 ,  H02M7/00 ,  H02M7/5387 ,  H02P27/06

CPC classification number: H01L29/0634 ,  H01L21/0223 ,  H01L21/02529 ,  H01L21/046 ,  H01L21/0485 ,  H01L21/049 ,  H01L23/3121 ,  H01L23/49562 ,  H01L24/48 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/417 ,  H01L29/4236 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H02M7/003 ,  H02M7/5387 ,  H01L21/02255 ,  H01L2224/48177 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/13091 ,  H02P27/06

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a main surface, a diode region of the first conductivity type formed in a surface layer portion of the main surface of the semiconductor layer, a carrier trapping region including crystal defects and formed along a peripheral edge of the diode region in the surface layer portion of the main surface of the semiconductor layer, and an anode electrode formed on the main surface of the semiconductor layer and forming a Schottky junction with the diode region.