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    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
    21.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20120144273A1

    公开(公告)日：2012-06-07

    申请号：US13372095

    申请日：2012-02-13

    Applicant: Hironori UCHIKAWA ,  Tatsuyuki Ishikawa ,  Mitsuaki Honma

    Inventor： Hironori UCHIKAWA ,  Tatsuyuki Ishikawa ,  Mitsuaki Honma

    IPC: H03M13/05 ,  G06F11/10

    CPC classification number: G11C29/52 ,  G06F11/1072 ,  G11C16/04 ,  G11C16/0483 ,  G11C29/00 ,  G11C2029/0411 ,  G11C2211/5641 ,  G11C2211/5643

    Abstract: A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.

    Abstract translation: 非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储N位（N≥2）的信息的多个存储单元。 奇偶校验数据加法器电路将用于纠错的奇偶校验数据添加到要存储在存储单元阵列中的每个特定数据位。 帧转换器电路将包含数据位和奇偶校验数据的帧数据均匀地分割成N个子帧数据。 编程电路将分割成N个的子帧数据存储在对应于N位信息的N个子页中。

    METHOD FOR READING A MULTILEVEL CELL IN A NON-VOLATILE MEMORY DEVICE
    22.
    发明申请
    METHOD FOR READING A MULTILEVEL CELL IN A NON-VOLATILE MEMORY DEVICE 有权
    在非易失性存储器件中读取多个单元的方法

    公开(公告)号：US20110179218A1

    公开(公告)日：2011-07-21

    申请号：US13073317

    申请日：2011-03-28

    Applicant: Chang Wan Ha

    Inventor： Chang Wan Ha

    IPC: G06F12/00

    CPC classification number: G06F12/0246 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5641 ,  G11C2211/5643 ,  G11C2211/5646

    Abstract: A non-volatile memory device has a memory array comprising a plurality of memory cells. The array can operate in either a multilevel cell or single level cell mode and each cell has a lower page and an upper page of data. The memory device has a data latch for storing flag data and a cache latch coupled to the data latch. A read method comprises initiating a lower page read of a memory cell and reading, from the data latch, flag data that indicates whether a lower page read operation is necessary.

    Abstract translation: 非易失性存储器件具有包括多个存储器单元的存储器阵列。 阵列可以在多电平单元或单电平单元模式下工作，并且每个单元都具有较低的页面和较高的数据页面。 存储器件具有用于存储标志数据的数据锁存器和耦合到数据锁存器的高速缓存锁存器。 读取方法包括启动存储器单元的下页读取并从数据锁存器读取指示是否需要下页读取操作的标志数据。

    Adaptive algorithm in cache operation with dynamic data latch requirements
    24.
    发明授权
    Adaptive algorithm in cache operation with dynamic data latch requirements 有权
    自适应算法在缓存操作中具有动态数据锁存要求

    公开(公告)号：US07961512B2

    公开(公告)日：2011-06-14

    申请号：US12051462

    申请日：2008-03-19

    Applicant: Yan Li ,  Anne Pao-Ling Koh

    Inventor： Yan Li ,  Anne Pao-Ling Koh

    IPC: G11C11/34

    CPC classification number: G11C16/10 ,  G06F12/0855 ,  G06F2212/2022 ,  G11C7/1039 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2207/2245 ,  G11C2211/5623 ,  G11C2211/5642 ,  G11C2211/5643

    Abstract: A non-volatile memory can perform a first operation (such as a write, for example) on a designated group of one or more addressed pages using a first set of data stored in the corresponding set of data latches and also receive a request for a second operation (such as a read, for example) that also uses some of these corresponding data latches with a second set of data. During the first operation, when at least one latch of each set of the corresponding become available for the second operation, the memory whether there are a sufficient number of the corresponding set of data latches to perform the second operation during the first operation; if not, the second operation is delayed. The memory subsequently can perform the second operation during the first operation when a sufficient number of latches become available; and if, in response to determining whether there are a sufficient number of the corresponding set of data latches to perform the second operation it is determined that there are a sufficient number, performing the second operation during the first operation.

    Abstract translation: 非易失性存储器可以使用存储在相应的数据锁存器组中的第一组数据来执行一个或多个寻址页面的指定组上的第一操作（例如写入），并且还接收对 还使用具有第二组数据的这些相应的数据锁存器中的一些的第二操作（例如读取）。 在第一操作期间，当对应的每组的至少一个锁存器变得可用于第二操作时，存储器是否存在足够数量的对应的一组数据锁存器以在第一操作期间执行第二操作; 如果没有，则第二操作被延迟。 当足够数量的锁存器变得可用时，存储器随后可以在第一操作期间执行第二操作; 并且如果响应于确定是否存在足够数量的对应的数据锁存器组来执行第二操作，则确定存在足够的数量，在第一操作期间执行第二操作。

    High endurance non-volatile memory devices
    25.
    发明授权
    High endurance non-volatile memory devices 有权
    高耐久性非易失性存储器件

    公开(公告)号：US07953931B2

    公开(公告)日：2011-05-31

    申请号：US12035398

    申请日：2008-02-21

    Applicant: I-Kang Yu ,  David Q. Chow ,  Charles C. Lee ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

    Inventor： I-Kang Yu ,  David Q. Chow ,  Charles C. Lee ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

    IPC: G06F12/12

    CPC classification number: G06F13/161 ,  G06F12/0246 ,  G06F12/0862 ,  G06F12/123 ,  G06F2212/7203 ,  G11C11/5621 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2211/5641 ,  G11C2211/5643

    Abstract: High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

    Abstract translation: 描述了高耐久性非易失性存储器件（NVMD）。 高耐久性NVMD包括I / O接口，NVM控制器，CPU以及易失性存储器子系统和至少一个非易失性存储器（NVM）模块。 易失性存储器缓存子系统被配置为数据高速缓存子系统。 当NVMD适用于主机系统时，至少一个NVM模块被配置为数据存储器。 I / O接口被配置为从主机接收数据缓存子系统的传入数据，并将请求数据从数据缓存子系统发送到主机。 至少一个NVM模块可以包括至少第一和第二类型的NVM。 第一种类型包括SLC闪存，而第二种类型的MLC闪存。 NVM的第一种类型被配置为数据高速缓存子系统和第二类NVM之间的缓冲区。

    Method for reading a multilevel cell in a non-volatile memory device
    28.
    发明授权
    Method for reading a multilevel cell in a non-volatile memory device 有权
    用于读取非易失性存储器件中的多电平单元的方法

    公开(公告)号：US07917685B2

    公开(公告)日：2011-03-29

    申请号：US11417573

    申请日：2006-05-04

    Applicant: Chang Wan Ha

    Inventor： Chang Wan Ha

    IPC: G06F12/00 ,  G06F13/00

    CPC classification number: G06F12/0246 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5641 ,  G11C2211/5643 ,  G11C2211/5646

    Abstract: A non-volatile memory device has a memory array comprising a plurality of memory cells. The array can operate in either a multilevel cell or single level cell mode and each cell has a lower page and an upper page of data. The memory device has a data latch for storing flag data and a cache latch coupled to the data latch. A read method comprises initiating a lower page read of a memory cell and reading, from the data latch, flag data that indicates whether a lower page read operation is necessary.

    Abstract translation: 非易失性存储器件具有包括多个存储器单元的存储器阵列。 阵列可以在多电平单元或单电平单元模式下工作，并且每个单元都具有较低的页面和较高的数据页面。 存储器件具有用于存储标志数据的数据锁存器和耦合到数据锁存器的高速缓存锁存器。 读取方法包括启动存储器单元的下页读取并从数据锁存器读取指示是否需要下页读取操作的标志数据。

    Page buffer for nonvolatile memory device
    30.
    发明授权
    Page buffer for nonvolatile memory device 有权
    非易失性存储器件的页缓冲器

    公开(公告)号：US07729177B2

    公开(公告)日：2010-06-01

    申请号：US11759649

    申请日：2007-06-07

    Applicant: Dae Sik Song ,  Jaeseok Park ,  Jacopo Mulatti

    Inventor： Dae Sik Song ,  Jaeseok Park ,  Jacopo Mulatti

    IPC: G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C7/10 ,  G11C7/06

    CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643

    Abstract: A nonvolatile memory device implements a program routine followed by a program-verify routine when recording or modifying stored data. The nonvolatile memory device may include an array of memory cells for storing data, a sense node, and a gating circuit for selectively connecting a bitline of the array of memory cells to the sense node. The nonvolatile memory device may also include a page buffer coupled to the sense node. The page buffer may include a main latch for storing data to be written in the nonvolatile memory device, a cache latch for storing data supplied on an input line of the nonvolatile memory device to be transferred in the main latch through a source liner and a temporary static latch connected to the main latch through the source line and to the cache latch through an auxiliary switch and for transferring data between the main latch and the cache latch. The cache latch may be isolated from the source line during execution of the program routine and of the program-verify routine.

    Abstract translation: 非易失性存储器件在记录或修改存储的数据时实现程序例程，随后是程序验证程序。 非易失性存储器件可以包括用于存储数据的存储器单元阵列，感测节点和用于选择性地将存储器单元阵列的位线连接到感测节点的选通电路。 非易失性存储器件还可以包括耦合到感测节点的页缓冲器。 页面缓冲器可以包括用于存储要写入非易失性存储器件的数据的主锁存器，用于存储提供在非易失性存储器件的输入线上的数据的高速缓冲存储器，用于通过源衬垫传输到主锁存器中， 静态锁存器通过源极线连接到主锁存器，并通过辅助开关连接到高速缓存锁存器，并用于在主锁存器和高速缓存锁存器之间传送数据。 在执行程序例程和程序验证程序期间，高速缓存锁存器可以与源线隔离。

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