公开(公告)号：US20130265837A1

公开(公告)日：2013-10-10

申请号：US13710504

申请日：2012-12-11

Applicant: Yong Jin Kwon ,  Kwang Jin Lee ,  Hye-Jin Kim

Inventor： Yong Jin Kwon ,  Kwang Jin Lee ,  Hye-Jin Kim

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028 ,  G11C2013/0088

Abstract: A non-volatile memory device includes a set pulse generator configured to generate a set pulse, a reset pulse generator configured to generate a reset pulse based on the set pulse, and a write driver block configured to write second data to a second non-volatile memory cell using the reset pulse, while writing first data to a first non-volatile memory cell using the set pulse.

Abstract translation: 非易失性存储器件包括被配置为产生置位脉冲的置位脉冲发生器，被配置为基于所设置的脉冲产生复位脉冲的复位脉冲发生器，以及被配置为将第二数据写入第二非易失性的写入驱动器块 使用复位脉冲的存储单元，同时使用设定脉冲将第一数据写入第一非易失性存储单元。

公开(公告)号：US08526223B2

公开(公告)日：2013-09-03

申请号：US13655666

申请日：2012-10-19

Applicant: Hye-jin Kim ,  Kwang-jin Lee ,  Du-eung Kim

Inventor： Hye-jin Kim ,  Kwang-jin Lee ,  Du-eung Kim

IPC: G11C11/00

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.

Abstract translation: 操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选PRAM单元中，其中所述程序操作包括多个顺序程序循环。 该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

公开(公告)号：US08506722B2

公开(公告)日：2013-08-13

申请号：US13265148

申请日：2010-04-19

Applicant: Kwang-Jin Lee

Inventor： Kwang-Jin Lee

IPC: B08B5/00

CPC classification number: B01D65/02 ,  B01D63/02 ,  B01D2315/06 ,  B01D2321/04 ,  B01D2321/162 ,  B01D2321/168 ,  B01D2321/185

Abstract: A method for cleaning a filtering membrane, contaminated by contaminants including inorganic and organic materials during a fluid-filtering process, is disclosed, the method comprises cleaning the filtering membrane by using a first cleaning solution of pH 6˜9 so as to remove the organic material from the filtering membrane; and cleaning the filtering membrane by using a second acid cleaning solution so as to remove the inorganic material from the filtering membrane, wherein the cleaning method of the present invention uses the first cleaning solution having pH 6˜9 instead of a strong-alkaline cleaning solution so as to prevent the filtering membrane from being damaged, and also uses the cleaning solution maintained at a relatively low temperature instead of hot water so as to improve economical efficiency by reduction of energy consumption.

Abstract translation: 公开了一种在流体过滤过程中清洁被污染物包括无机和有机材料的过滤膜的方法，该方法包括使用pH6〜9的第一清洗液清洗过滤膜，以除去有机物 过滤膜材料; 并利用第二种酸性清洗液清洗过滤膜，以从过滤膜中除去无机材料，其中本发明的清洗方法使用pH6〜9的第一清洗液，而不是强碱性清洗液 以防止过滤膜被损坏，并且还使用维持在较低温度而不是热水的清洗溶液，从而通过降低能量消耗来提高经济效率。

公开(公告)号：US08218360B2

公开(公告)日：2012-07-10

申请号：US12582880

申请日：2009-10-21

Applicant: Kwang-Jin Lee ,  Young-kug Moon ,  Young-pil Kim

Inventor： Kwang-Jin Lee ,  Young-kug Moon ,  Young-pil Kim

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/004 ,  G11C7/1018 ,  G11C8/18 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004

Abstract: Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line of the phase-change or resistance-change memory cell array and to insert a dummy burst in which no data is read when a first boundary crossing occurs during a burst mode operation. Related methods of operating phase-change and/or resistance-change random access memory devices in burst mode are also provided.

Abstract translation: 提供了相变和电阻变化随机存取存储器件，其包括相变或电阻变化存储单元阵列和被配置为放大从相变存储单元阵列读取的数据的读出放大器。 这些随机存取存储器件被配置为从相变或电阻变化存储单元阵列的第一字线读取数据，并且在突发模式操作期间发生第一边界交叉时插入其中没有读取数据的虚拟脉冲串 。 还提供了以突发模式操作相变和/或电阻变化随机存取存储器件的相关方法。

公开(公告)号：US08190968B2

公开(公告)日：2012-05-29

申请号：US13099640

申请日：2011-05-03

Applicant: Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

Inventor： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

IPC: H03M13/00

CPC classification number: G06F11/1008 ,  G06F11/1076 ,  G11C8/04 ,  G11C8/12

Abstract: A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.

Abstract translation: 半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。 存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。 模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。 奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。 数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为 检测并输出校正的读取数据。

公开(公告)号：US08174878B2

公开(公告)日：2012-05-08

申请号：US13053471

申请日：2011-03-22

Applicant: Joon-Min Park ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

Inventor： Joon-Min Park ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2213/72

Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

Abstract translation: 提供了一种非易失性存储器及其相关编程方法。 非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。 写电路被配置为在第一程序操作期间使用内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二程序操作期间将第二逻辑状态数据写入第二组存储器单元 外部提供的升压电压。

公开(公告)号：US08143653B2

公开(公告)日：2012-03-27

申请号：US12619016

申请日：2009-11-16

Applicant: Woo-Yeong Cho ,  Jong-Soo Seo ,  Young-Kug Moon ,  Jun-Soo Bae ,  Kwang-Jin Lee

Inventor： Woo-Yeong Cho ,  Jong-Soo Seo ,  Young-Kug Moon ,  Jun-Soo Bae ,  Kwang-Jin Lee

IPC: H01L29/66

CPC classification number: G11C13/0064 ,  G11C7/04 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2213/72 ,  H01L27/2409 ,  H01L29/868 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

Abstract: A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit.

Abstract translation: 提供了相变随机存取存储器件。 相变随机存取存储器件包括连接到写入电路和读取电路的全局位线，每个连接到多个相变存储器单元的多个局部位线，以及选择性地连接全局位线的多个列选择晶体管 对于多个局部位线中的每一个，每个列选择晶体管具有根据其与写入电路和读取电路的距离而变化的电阻。

公开(公告)号：US08134866B2

公开(公告)日：2012-03-13

申请号：US12652842

申请日：2010-01-06

Applicant: Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho ,  Woo-Yeong Cho ,  Hye-Jin Kim

Inventor： Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho ,  Woo-Yeong Cho ,  Hye-Jin Kim

IPC: G11C11/00

CPC classification number: G11C8/10 ,  G11C5/143 ,  G11C5/145 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078

Abstract: A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.

Abstract translation: 一种方法对相变存储器件进行编程。 该方法包括接收所选存储单元的程序数据; 基于参考单元产生偏置电压; 通过向所选择的存储器单元提供由偏置电压确定的验证电流来感测存储在所选存储单元中的读取数据; 确定读取的数据是否与节目数据相同; 并且一旦确定所选存储器单元中的一个或多个的程序数据与相应的读取数据不同，则迭代地向一个或多个所选择的存储器单元施加写入电流。

公开(公告)号：US07961504B2

公开(公告)日：2011-06-14

申请号：US12724679

申请日：2010-03-16

Applicant: Hye-jin Kim ,  Kwang-jin Lee ,  Du-eung Kim

Inventor： Hye-jin Kim ,  Kwang-jin Lee ,  Du-eung Kim

IPC: G11C11/00

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.

Abstract translation: 操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选PRAM单元中，其中所述程序操作包括多个顺序程序循环。 该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

公开(公告)号：US07949928B2

公开(公告)日：2011-05-24

申请号：US11773214

申请日：2007-07-03

Applicant: Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

Inventor： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

IPC: G11C29/00

CPC classification number: G06F11/1008 ,  G06F11/1076 ,  G11C8/04 ,  G11C8/12

Abstract: A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.

Abstract translation: 半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。 存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。 模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。 奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。 数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为 检测并输出校正的读取数据。