公开(公告)号：US20140250280A1

公开(公告)日：2014-09-04

申请号：US14283117

申请日：2014-05-20

Applicant: Micron Technology, Inc.

Inventor： Federico Pio

IPC: G11C14/00

CPC classification number: G11C5/147 ,  G06F12/0246 ,  G06F21/60 ,  G06F2212/7204 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C11/5621 ,  G11C11/5671 ,  G11C14/0063 ,  G11C14/009 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/107 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

Abstract: A method is provided for accessing a memory device. The method includes programming data in a plurality of cells of the memory device in a first programming operation. The first programming operation uses a first memory instruction including at least one first parameter representative of at least one first threshold voltage value for said programming. The method further includes re-programming at least a portion of the data in the plurality of cells in a second programming operation. The second programming operation uses a second memory instruction including at least one second parameter representative of at least one second threshold voltage value for said re-programming, wherein said re-programming provides bit manipulation of the portion of the data.

Abstract translation: 提供了一种访问存储器件的方法。 该方法包括在第一编程操作中在存储器件的多个单元中编程数据。 第一编程操作使用包括代表用于所述编程的至少一个第一阈值电压值的至少一个第一参数的第一存储器指令。 该方法还包括在第二编程操作中对多个单元中的数据的至少一部分进行重新编程。 第二编程操作使用包括表示用于所述重新编程的至少一个第二阈值电压值的至少一个第二参数的第二存储器指令，其中所述重新编程提供对所述数据的该部分的位操作。

公开(公告)号：US08817536B2

公开(公告)日：2014-08-26

申请号：US12006228

申请日：2007-12-31

Applicant: Andreas Scade ,  David Still ,  James Allen ,  Jay Ashokkumar ,  Jaskarn Singh Johal

Inventor： Andreas Scade ,  David Still ,  James Allen ,  Jay Ashokkumar ,  Jaskarn Singh Johal

IPC: G11C14/00 ,  G11C11/00

CPC classification number: G11C14/00 ,  G11C14/0063

Abstract: A memory circuit includes a controlled current source coupled to an input to a nonvolatile cell, and a second controlled current source coupled to a volatile cell, the volatile cell coupled to receive current from the controlled current source via the nonvolatile cell.

Abstract translation: 存储器电路包括耦合到非易失性单元的输入的受控电流源和耦合到易失性单元的第二受控电流源，所述易失性单元被耦合以经由非易失性单元从受控电流源接收电流。

公开(公告)号：US20140218996A1

公开(公告)日：2014-08-07

申请号：US14246548

申请日：2014-04-07

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： MANUEL ANTONIO D'ABREU ,  STEPHEN SKALA ,  DIMITRIS PANTELAKIS ,  RADHAKRISHNAN NAIR ,  DEEPAK PANCHOLI

IPC: G11C5/02

CPC classification number: G11C5/02 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1072 ,  G06F13/1668 ,  G11C14/0063 ,  G11C16/10 ,  G11C16/26 ,  G11C29/04 ,  G11C2029/0411 ,  Y02D10/14

Abstract: An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface.

Abstract translation: 一种装置包括包括三维（3D）存储器的半导体器件。 3D存储器包括布置在衬底上方多个物理层的多个存储单元。 3D存储器包括与多个存储器单元的操作相关联的电路并且包括串行器/解串器接口。

公开(公告)号：US20140050025A1

公开(公告)日：2014-02-20

申请号：US13965031

申请日：2013-08-12

Applicant: Hsing-Ya Tsao ,  Peter Wung Lee

Inventor： Hsing-Ya Tsao ,  Peter Wung Lee

IPC: G11C14/00

CPC classification number: G11C14/0063 ,  G11C14/00 ,  G11C16/04 ,  G11C16/0433 ,  G11C16/16

Abstract: This invention discloses a low-voltage fast-write 12T or 14T PMOS NVSRAM cell structure which comprises a 6T LV SRAM cell and one pairs of two 3T or 4T HV PMOS Flash strings. Due to reverse threshold voltage definition of PMOS and NMOS flash cell, this PMOS NVSRAM cell has the advantage over the NMOS NVSRAM cell to have the same data polarity between SRAM and Flash pairs during the data writing operation. In addition, this PMOS NVSRAM's PMOS Flash cell uses similar low-current FN-tunneling scheme as NMOS NVSRAM, thus the fast data program and erase can be achieved in a big density up to 100 Mb simultaneously. As a result, low power voltage operation of NVSRAM with 1.2V VDD can be much easier to be designed without coupling the FSL line to any VDD level during the flash data loading into SRAM cell during a power-on period.

Abstract translation: 本发明公开了一种低电压快写12T或14T PMOS NVSRAM单元结构，其包括6T LV SRAM单元和一对两个3T或4T HV PMOS闪存串。 由于PMOS和NMOS闪存单元的反向阈值电压分辨率，该PMOS NVSRAM单元在数据写入操作期间具有超过NMOS NVSRAM单元在SRAM和闪存对之间具有相同数据极性的优势。 此外，该PMOS NVSRAM的PMOS闪存单元使用与NMOS NVSRAM类似的低电流FN隧穿方案，因此快速数据编程和擦除可以同时实现高达100 Mb的大密度。 因此，在上电期间闪存数据加载到SRAM单元期间，具有1.2V VDD的NVSRAM的低功耗电压操作可以轻松设计，无需将FSL线耦合到任何VDD电平。

公开(公告)号：US08542514B1

公开(公告)日：2013-09-24

申请号：US12242285

申请日：2008-09-30

Applicant: Sethuraman Lakshminarayanan ,  Myongseob Kim

Inventor： Sethuraman Lakshminarayanan ,  Myongseob Kim

IPC: G11C5/06

CPC classification number: G11C5/06 ,  G11C14/0054 ,  G11C14/0063

Abstract: A memory structure and method to fabricate the same is described. The memory structure includes a first memory cell having a first pair of non-volatile portions. The memory structure also includes a second memory cell having a second pair of non-volatile portions. The first and second pairs of non-volatile portions are disposed in an inter-locking arrangement.

Abstract translation: 描述了制造它的记忆体结构和方法。 存储器结构包括具有第一对非易失性部分的第一存储单元。 存储器结构还包括具有第二对非易失性部分的第二存储器单元。 第一和第二对非易失性部分以互锁方式设置。

公开(公告)号：US20130222033A1

公开(公告)日：2013-08-29

申请号：US13854176

申请日：2013-04-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H03K3/286

CPC classification number: H03K3/356104 ,  G11C7/04 ,  G11C14/0063 ,  G11C16/045 ,  G11C2211/4016 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/28202 ,  H01L21/28211 ,  H01L27/105 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/6659 ,  H03K3/0375 ,  H03K3/286 ,  H03K3/356 ,  H03K3/356121 ,  H03K3/356173

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.

Abstract translation: 为了提供使用非易失性锁存电路的新型非易失性锁存电路和半导体器件，非易失性锁存电路包括具有环形结构的锁存部分，其中第一元件的输出电连接到第二元件的输入端，输出端 的第二元件电连接到第一元件的输入端; 以及用于保持锁存部分的数据的数据保持部分。 在数据保持部分中，使用使用氧化物半导体作为形成沟道形成区域的半导体材料的晶体管作为开关元件。 此外，还包括与晶体管的源电极或漏电极电连接的反相器。 利用晶体管，保持在锁存部分中的数据可以写入逆变器的栅极电容器或单独提供的电容器。

公开(公告)号：US20130069134A1

公开(公告)日：2013-03-21

申请号：US13608436

申请日：2012-09-10

Applicant: Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

Inventor： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

IPC: H01L27/11

CPC classification number: H01L29/42332 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1104 ,  H01L29/7881

Abstract: In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

Abstract translation: 在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极， 第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。 在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜 ，第四浮栅，第六绝缘膜和第二控制栅极。

公开(公告)号：US20120213027A1

公开(公告)日：2012-08-23

申请号：US13216546

申请日：2011-08-24

Applicant: James D. Allan ,  Jayant Ashokkumar

Inventor： James D. Allan ,  Jayant Ashokkumar

IPC: G11C5/14

CPC classification number: G11C7/20 ,  G11C14/00 ,  G11C14/0063

Abstract: A system and method for resetting semiconductor memory is disclosed. The present invention uses an array reset circuit to independently drive the bit lines of a volatile memory cell high or low so as to reset either a single memory cell or all memory cells in an array with all 0's or all 1's.

Abstract translation: 公开了一种用于复位半导体存储器的系统和方法。 本发明使用阵列复位电路来独立地驱动易失性存储器单元的高位或低位的位线，以将单个存储器单元或具有全0或全部1的阵列中的所有存储单元复位。

公开(公告)号：US20110261620A1

公开(公告)日：2011-10-27

申请号：US13175893

申请日：2011-07-04

Applicant: Ping-Chia Shih ,  Chung-Chin Shih

Inventor： Ping-Chia Shih ,  Chung-Chin Shih

IPC: G11C14/00

CPC classification number: G11C14/0063

Abstract: A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interrupted, the non-volatile circuit can provide data backup using an inverter circuit and a non-volatile erasable programmable memory (NVEPM) circuit, thereby retaining data previously stored in the volatile circuit.

公开(公告)号：US08018768B2

公开(公告)日：2011-09-13

申请号：US12542711

申请日：2009-08-18

Applicant: Ping-Chia Shih ,  Chung-Chin Shih

Inventor： Ping-Chia Shih ,  Chung-Chin Shih

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C14/0063

Abstract: A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interrupted, the non-volatile circuit can provide data backup using an inverter circuit and a non-volatile erasable programmable memory (NVEPM) circuit, thereby retaining data previously stored in the volatile circuit.

Abstract translation: 非易失性静态随机存取存储器（NVSRAM）装置包括易失性电路和非易失性电路。 在提供外部电源的正常操作下，易失性电路可以提供快速的数据访问。 当电源以某种方式中断时，非易失性电路可以使用逆变器电路和非易失性可擦除可编程存储器（NVEPM）电路提供数据备份，从而保留先前存储在易失性电路中的数据。