公开(公告)号：US20130103891A1

公开(公告)日：2013-04-25

申请号：US13331773

申请日：2011-12-20

Applicant: ERAN SHARON ,  IDAN ALROD

Inventor： ERAN SHARON ,  IDAN ALROD

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/40 ,  G11C16/3495 ,  G11C2211/5647 ,  Y02D10/13

Abstract: Methods described in the present disclosure may be based on a direct transformation of original data to “shaped” data. The disclosed methods may be performed “on-the-fly” and the disclosed methods may utilize an inherent redundancy in compressible data in order to achieve endurance enhancement and error reduction. In a particular example, a method comprises generating a first portion of output data by applying a mapping of input bit sequences to output bit sequences to a first portion of input data, updating the mapping of the input bit sequences to the output bit sequences based on the first portion of the input data to generate an updated mapping, reading a second portion of the input data, and generating a second portion of the output data by applying the updated mapping of the input bit sequences to the output bit sequences to the second portion of the input data.

Abstract translation: 本公开中描述的方法可以基于将原始数据直接转换为“成形”数据。 所公开的方法可以“即时”执行，并且所公开的方法可以利用可压缩数据中的固有冗余，以便实现耐久性增强和错误减少。 在特定示例中，一种方法包括通过将输入比特序列的映射应用于输入比特序列到输入数据的第一部分来生成输出数据的第一部分，基于以下方式更新输入比特序列到输出比特序列的映射： 输入数据的第一部分以产生更新的映射，读取输入数据的第二部分，以及通过将输入比特序列的更新映射应用于输出比特序列到第二部分来生成输出数据的第二部分 的输入数据。

公开(公告)号：US09947071B2

公开(公告)日：2018-04-17

申请号：US14742291

申请日：2015-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Karthik Ramani ,  Abhinav Golas ,  John W. Brothers

IPC: G06K9/52 ,  G06T9/00 ,  G06T1/60 ,  G06T11/40

CPC classification number: G06T1/60 ,  G06F2212/40 ,  G06K9/527 ,  G06T11/40 ,  G09G5/393 ,  G09G5/395 ,  G09G2340/02 ,  G09G2350/00 ,  G09G2360/121 ,  G09G2360/122 ,  G09G2360/18

Abstract: A graphics system supports variable rate compression and decompression of texture data and color data. An individual block of data is analyzed to determine a compression data type from a plurality of different compression data types having different compression lengths. The compression data types may include a compression data type for a block having a constant (flat) pixel value over n×n pixels, compression data type in which a subset of 3 or 4 values represents a plane or gradient, and wavelet or other compression type to represent higher frequency content. Additionally, metadata indexing provides information to map between an uncompressed address to a compressed address. To reduce the storage requirement, the metadata indexing permits two or more duplicate data blocks to reference the same piece of compressed data.

公开(公告)号：US20170345125A1

公开(公告)日：2017-11-30

申请号：US15676936

申请日：2017-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Abhinav Golas ,  Sangheon Lee ,  Vandit Mehra

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F2212/40 ,  G06K9/527 ,  G06T1/20 ,  G06T11/40

Abstract: A method of variable rate compression of image data in an image pipeline of a graphics processing system, the method includes identifying, by a processor of the graphics processing system, a set of cTiles associated with the image data, each cTile including a plurality of pixels, for each cTile of the set of cTiles identifying, by the processor, a pivot pixel from among the plurality of pixels, identifying, by the processor, a compression type of the cTile by comparing, bit-by-bit , pixels within the cTile with the pivot pixel, and compressing, by the processor, the cTile based on the identified compression type, and generating, by the processor, a metadata entry associated with the set of cTiles, the metadata entry indicating the compression type of each one of the set of cTiles and defining a mapping between an uncompressed address space of the set of cTiles and a compressed address space.

公开(公告)号：US20170116121A1

公开(公告)日：2017-04-27

申请号：US14997344

申请日：2016-01-15

Applicant: Oracle International Corporation

Inventor： TODD LITTLE ,  XUGANG SHEN ,  JIM YONGSHUN JIN ,  JESSE HOU

IPC: G06F12/08 ,  G06F9/46

CPC classification number: H04L67/2842 ,  G06F9/467 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0897 ,  G06F12/10 ,  G06F2212/154 ,  G06F2212/40 ,  G06F2212/60 ,  G06F2212/62 ,  H04L67/1097 ,  H04L67/16 ,  H04L67/20 ,  H04L67/2823 ,  H04L67/288

Abstract: In accordance with an embodiment, described herein is a system and method for providing distributed caching in a transactional processing environment. The caching system can include a plurality of layers that provide a caching feature for a plurality of data types, and can be configured for use with a plurality of caching providers. A common data structure can be provided to store serialized bytes of each data type, and architecture information of a source platform executing a cache-setting application, so that a cache-getting application can use the information to convert the serialized bytes to a local format. A proxy server can be provided to act as a client to a distributed in-memory grid, and advertise services to a caching client, where each advertised service can match a cache in the distributed in-memory data grid, such as Coherence. The caching system can be used to cache results from a service.

公开(公告)号：US20160350224A1

公开(公告)日：2016-12-01

申请号：US14891338

申请日：2014-12-13

Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD

Inventor： RODNEY E. HOOKER ,  DOUGLAS R. REED

IPC: G06F12/0855 ,  G06F12/0877 ,  G06F12/0897

CPC classification number: G06F12/0855 ,  G06F9/38 ,  G06F9/382 ,  G06F9/467 ,  G06F9/524 ,  G06F12/0877 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/40

Abstract: A microprocessor comprises a cache including a tag array; a tag pipeline that arbitrates access to the tag array; and a pattern detector. The pattern detector comprises a register; a decoder that decodes transaction type identifiers of tagpipe arbs advancing through the tag pipeline; and an accumulator that accumulates into the register the transaction type identifiers of a plurality of tagpipe arbs that advance through the tag pipeline.

Abstract translation: 微处理器包括包括标签阵列的高速缓存器; 标记流水线，用于仲裁对标签数组的访问; 和图案检测器。 模式检测器包括寄存器; 解码器，其解码通过标签管道前进的标记栏的交易类型标识符; 以及累加器，其向所述寄存器中累积通过所述标签流水线前进的多个标记栏的交易类型标识符。

公开(公告)号：US20150379684A1

公开(公告)日：2015-12-31

申请号：US14742291

申请日：2015-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Karthik RAMANI ,  Abhinav GOLAS ,  John W. BROTHERS

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F2212/40 ,  G06K9/527 ,  G06T11/40 ,  G09G5/393 ,  G09G5/395 ,  G09G2340/02 ,  G09G2350/00 ,  G09G2360/121 ,  G09G2360/122 ,  G09G2360/18

Abstract: A graphics system supports variable rate compression and decompression of texture data and color data. An individual block of data is analyzed to determine a compression data type from a plurality of different compression data types having different compression lengths. The compression data types may include a compression data type for a block having a constant (flat) pixel value over n×n pixels, compression data type in which a subset of 3 or 4 values represents a plane or gradient, and wavelet or other compression type to represent higher frequency content. Additionally, metadata indexing provides information to map between an uncompressed address to a compressed address. To reduce the storage requirement, the metadata indexing permits two or more duplicate data blocks to reference the same piece of compressed data.

Abstract translation: 图形系统支持纹理数据和颜色数据的可变速率压缩和解压缩。 分析单个数据块以从具有不同压缩长度的多个不同压缩数据类型确定压缩数据类型。 压缩数据类型可以包括用于具有超过n×n个像素的恒定（平坦）像素值的块的压缩数据类型，其中3或4个值的子集表示平面或梯度的压缩数据类型，以及小波或其他压缩 类型表示较高的频率内容。 另外，元数据索引提供了在未压缩地址与压缩地址之间进行映射的信息。 为了减少存储要求，元数据索引允许两个或多个重复数据块引用同一压缩数据。

公开(公告)号：US20150309865A1

公开(公告)日：2015-10-29

申请号：US14500515

申请日：2014-09-29

Applicant: SK hynix Inc.

Inventor： Jae Woo KIM ,  Joong Hyun AN ,  Kwang Hyun KIM

IPC: G06F11/10 ,  G06F13/28

CPC classification number: G06F11/1008 ,  G06F9/30192 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0835 ,  G06F12/1081 ,  G06F13/28 ,  G06F2212/40 ,  G06F2212/403 ,  G06F2213/28 ,  G06F2213/2802 ,  Y02D10/14

Abstract: A data storage device includes a storage memory device; a signal generation block suitable for generating control signals to be provided to the storage memory device; and an error correction code (ECC) block suitable for ECC-encoding data to be stored in the storage memory device, wherein the ECC block operates before the signal generation block.

Abstract translation: 数据存储装置包括存储存储装置; 信号生成块，适于产生要提供给存储存储器件的控制信号; 以及适用于要存储在存储存储器件中的ECC编码数据的纠错码（ECC）块，其中ECC块在信号生成块之前操作。

公开(公告)号：US08799559B2

公开(公告)日：2014-08-05

申请号：US13331773

申请日：2011-12-20

Applicant: Eran Sharon ,  Idan Alrod

Inventor： Eran Sharon ,  Idan Alrod

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/40 ,  G11C16/3495 ,  G11C2211/5647 ,  Y02D10/13

Abstract: Methods described in the present disclosure may be based on a direct transformation of original data to “shaped” data. In a particular example, a method comprises generating a first portion of output data by applying a mapping of input bit sequences to output bit sequences to a first portion of input data, updating the mapping of the input bit sequences to the output bit sequences based on the first portion of the input data to generate an updated mapping, reading a second portion of the input data, and generating a second portion of the output data by applying the updated mapping of the input bit sequences to the output bit sequences to the second portion of the input data.

Abstract translation: 本公开中描述的方法可以基于将原始数据直接转换为“成形”数据。 在特定示例中，一种方法包括通过将输入比特序列的映射应用于输入比特序列到输入数据的第一部分来生成输出数据的第一部分，基于以下方式更新输入比特序列到输出比特序列的映射： 输入数据的第一部分以产生更新的映射，读取输入数据的第二部分，以及通过将输入比特序列的更新映射应用于输出比特序列到第二部分来生成输出数据的第二部分 的输入数据。

公开(公告)号：US20130297853A1

公开(公告)日：2013-11-07

申请号：US13464084

申请日：2012-05-04

Applicant: Ganesh Balakrishnan ,  Anil Krishna

Inventor： Ganesh Balakrishnan ,  Anil Krishna

IPC: G06F12/00

CPC classification number: G06F12/0866 ,  G06F12/0246 ,  G06F2212/222 ,  G06F2212/40 ,  Y02D10/13

Abstract: In a method for storing data in a flash memory array, the flash memory array includes a plurality of physical pages. The method includes receiving a request to perform a data access operation through a communication bus. The request includes data and a logical page address. The method further includes allocating one or more physical pages of the flash memory array to perform the data access operation. The method further includes, based on a historical usage data of the flash memory array, selectively encoding the data contained in the logical page into the one or more physical pages.

Abstract translation: 在将数据存储在闪存阵列中的方法中，闪存阵列包括多个物理页。 该方法包括通过通信总线接收执行数据访问操作的请求。 该请求包括数据和逻辑页面地址。 该方法还包括分配闪存阵列的一个或多个物理页面以执行数据访问操作。 该方法还包括基于闪速存储器阵列的历史使用数据，选择性地将包含在逻辑页面中的数据编码到一个或多个物理页面中。