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    PROCESSOR WITH PROGRAMMABLE PREFETCHER
    1.
    发明申请
    PROCESSOR WITH PROGRAMMABLE PREFETCHER 审中-公开

    公开(公告)号：US20170161196A1

    公开(公告)日：2017-06-08

    申请号：US15372045

    申请日：2016-12-07

    Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

    Inventor： G. GLENN HENRY ,  RODNEY E. HOOKER ,  TERRY PARKS ,  DOUGLAS R. REED

    IPC: G06F12/0862 ,  G06F12/0855

    CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/3802 ,  G06F12/0855 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6028

    Abstract: A processor including a front end, at least one load pipeline, and a memory system that further includes a programmable prefetcher for prefetching information from an external memory. The front end converts fetched program instructions into microinstructions including load microinstructions and dispatches microinstructions for execution. The load pipeline executes dispatched load microinstructions and provides load requests to the memory system. The programmable prefetcher includes a load monitor, a programmable prefetch engine, and a prefetch requester. The load monitor tracks the load requests. The prefetch engine is configured to be programmed by at least one prefetch program to operate as a programmed prefetcher, such that during operation of the processor, the programmed prefetcher generates at least one prefetch address based on the load requests issued by the processor. The prefetch requester submits the at least one prefetch address to prefetch information from the memory system.

    CACHE REPLACEMENT POLICY THAT CONSIDERS MEMORY ACCESS TYPE
    2.
    发明申请
    CACHE REPLACEMENT POLICY THAT CONSIDERS MEMORY ACCESS TYPE 有权
    考虑到内存访问类型的缓存更换策略

    公开(公告)号：US20160350228A1

    公开(公告)日：2016-12-01

    申请号：US14890904

    申请日：2014-12-14

    Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

    Inventor： RODNEY E. HOOKER ,  DOUGLAS R. REED ,  JOHN MICHAEL GREER ,  COLIN EDDY ,  TERRY PARKS

    IPC: G06F12/0864 ,  G06F12/0877

    CPC classification number: G06F12/0864 ,  G06F8/4442 ,  G06F12/08 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/123 ,  G06F12/126 ,  G06F12/127 ,  G06F2212/1021 ,  G06F2212/604

    Abstract: An associative cache memory, comprising: an array of storage elements arranged as M sets by N ways; an allocation unit allocates the storage elements in response to memory accesses that miss in the cache memory. Each memory access selects a set. Each memory access has an associated memory access type (MAT) of a plurality of predetermined MATs. Each valid storage element has an associated MAT; a mapping that includes, for each MAT, a MAT priority. In response to a memory access that misses in the array, the allocation unit: determines a most eligible way and a second most eligible way of the selected set for replacement based on a replacement policy; and replaces the second most eligible way rather than the most eligible way when the MAT priority of the most eligible way is greater than the MAT priority of the second most eligible way.

    Abstract translation: 一种联想高速缓冲存储器，包括：通过N路布置成M组的存储元件的阵列; 分配单元响应于在高速缓冲存储器中错过的存储器访问来分配存储元件。 每个存储器访问选择一个集合。 每个存储器访问具有多个预定MAT的相关联的存储器访问类型（MAT）。 每个有效的存储元件都有一个相关的MAT; 对于每个MAT，包括MAT优先级的映射。 响应于在阵列中丢失的存储器访问，分配单元：基于替换策略确定所选择的集合的最符合资格的方式和第二最符合条件的替换方式; 并且最符合条件的方法的MAT优先级大于第二最符合条件的MAT优先级时，替代第二最符合条件的方式而不是最符合条件的方式。

    SET ASSOCIATIVE CACHE MEMORY WITH HETEROGENEOUS REPLACEMENT POLICY
    4.
    发明申请
    SET ASSOCIATIVE CACHE MEMORY WITH HETEROGENEOUS REPLACEMENT POLICY 有权
    使用异构替换策略设置相关的高速缓存存储器

    公开(公告)号：US20160357680A1

    公开(公告)日：2016-12-08

    申请号：US14890895

    申请日：2014-12-14

    Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

    Inventor： RODNEY E. HOOKER ,  DOUGLAS R. REED ,  JOHN MICHAEL GREER ,  COLIN EDDY

    IPC: G06F12/0864 ,  G06F12/128

    CPC classification number: G06F12/0864 ,  G06F8/4442 ,  G06F12/0846 ,  G06F12/127 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

    Abstract: A set associative cache memory, comprising: an array of storage elements arranged as M sets by N ways; an allocation unit that allocates the storage elements in response to memory accesses that miss in the cache memory. Each memory access selects a set; for each parcel of a plurality of parcels, a parcel specifier specifies: a subset of ways of the N ways included in the parcel. The subsets of ways of parcels associated with a selected set are mutually exclusive; a replacement scheme associated with the parcel from among a plurality of predetermined replacement schemes. For each memory access, the allocation unit: selects the parcel specifier in response to the memory access; and uses the replacement scheme associated with the parcel to allocate into the subset of ways of the selected set included in the parcel.

    Abstract translation: 一种组合关联高速缓冲存储器，包括：通过N路排列成M组的存储元件的阵列; 分配单元，其响应于在高速缓冲存储器中缺失的存储器访问来分配存储元件。 每个存储器访问选择一个集合; 对于多个宗地的每个宗地，宗地说明符指定：包裹中包含的N种方式的方式的子集。 与所选集相关联的包裹方式的子集是相互排斥的; 与多个预定替换方案中的包裹相关联的替换方案。 对于每个存储器访问，分配单元：响应于存储器访问选择包裹说明符; 并且使用与包裹相关联的替换方案来分配到包裹中包括的所选集合的方式的子集中。

    PATTERN DETECTOR FOR DETECTING HANGS
    5.
    发明申请
    PATTERN DETECTOR FOR DETECTING HANGS 有权
    用于检测HANGS的图案检测器

    公开(公告)号：US20160350224A1

    公开(公告)日：2016-12-01

    申请号：US14891338

    申请日：2014-12-13

    Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD

    Inventor： RODNEY E. HOOKER ,  DOUGLAS R. REED

    IPC: G06F12/0855 ,  G06F12/0877 ,  G06F12/0897

    CPC classification number: G06F12/0855 ,  G06F9/38 ,  G06F9/382 ,  G06F9/467 ,  G06F9/524 ,  G06F12/0877 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/40

    Abstract: A microprocessor comprises a cache including a tag array; a tag pipeline that arbitrates access to the tag array; and a pattern detector. The pattern detector comprises a register; a decoder that decodes transaction type identifiers of tagpipe arbs advancing through the tag pipeline; and an accumulator that accumulates into the register the transaction type identifiers of a plurality of tagpipe arbs that advance through the tag pipeline.

    Abstract translation: 微处理器包括包括标签阵列的高速缓存器; 标记流水线，用于仲裁对标签数组的访问; 和图案检测器。 模式检测器包括寄存器; 解码器，其解码通过标签管道前进的标记栏的交易类型标识符; 以及累加器，其向所述寄存器中累积通过所述标签流水线前进的多个标记栏的交易类型标识符。

    CACHE SYSTEM WITH A PRIMARY CACHE AND AN OVERFLOW CACHE THAT USE DIFFERENT INDEXING SCHEMES
    6.
    发明申请
    CACHE SYSTEM WITH A PRIMARY CACHE AND AN OVERFLOW CACHE THAT USE DIFFERENT INDEXING SCHEMES 审中-公开
    具有初级缓存的缓存系统和使用不同索引方案的溢出缓存

    公开(公告)号：US20160170884A1

    公开(公告)日：2016-06-16

    申请号：US14889113

    申请日：2014-12-12

    Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

    Inventor： COLIN EDDY ,  RODNEY E. HOOKER

    IPC: G06F12/08 ,  G06F12/12 ,  G06F12/10

    CPC classification number: G06F12/0811 ,  G06F12/0808 ,  G06F12/0864 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/123 ,  G06F2212/1021 ,  G06F2212/683

    Abstract: A cache memory system including a primary cache and an overflow cache that are searched together using a search address. The overflow cache operates as an eviction array for the primary cache. The primary cache is addressed using bits of the search address, and the overflow cache is addressed by a hash index generated by a hash function applied to bits of the search address. The hash function operates to distribute victims evicted from the primary cache to different sets of the overflow cache to improve overall cache utilization. A hash generator may be included to perform the hash function. A hash table may be included to store hash indexes of valid entries in the primary cache. The cache memory system may be used to implement a translation lookaside buffer for a microprocessor.

    Abstract translation: 包括使用搜索地址一起搜索的主缓存和溢出高速缓存的高速缓冲存储器系统。 溢出缓存作为主缓存的逐出数组。 使用搜索地址的比特来寻址主缓存，并且通过由应用于搜索地址的比特的哈希函数生成的哈希索引来寻址溢出缓存。 哈希函数用于将从主缓存逐出的受害者分发到不同的溢出缓存集，以提高整体缓存利用率。 可以包括散列生成器来执行散列函数。 可以包括散列表来存储主缓存中的有效条目的散列索引。 高速缓冲存储器系统可以用于实现微处理器的翻译后备缓冲器。

    CACHE MEMORY DIAGNOSTIC WRITEBACK
    10.
    发明申请
    CACHE MEMORY DIAGNOSTIC WRITEBACK 有权
    缓存记忆诊断写

    公开(公告)号：US20160293273A1

    公开(公告)日：2016-10-06

    申请号：US14890421

    申请日：2014-11-26

    Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

    Inventor： RODNEY E. HOOKER ,  STEPHAN GASKINS ,  DOUGLAS R. REED ,  JASON CHEN

    IPC: G11C29/38 ,  G11C29/44

    CPC classification number: G11C29/38 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0857 ,  G06F12/0864 ,  G06F2212/1024 ,  G06F2212/6042 ,  G11C29/44

    Abstract: A processor includes a cache memory having a plurality of entries. Each of the entries holds data of a cache line, a state of the cache line and a tag of the cache line. The cache memory includes an engine comprising one or more finite state machines. The processor also includes an interface to a bus over which the processor writes back modified cache lines from the cache memory to the system memory in response to encountering an architectural writeback and invalidate instruction. The processor also invalidates the state of the entries of the cache memory in response to encountering the architectural writeback and invalidate instruction. In response to being instructed to perform a cache diagnostic operation, for each entry of the entries, the engine writes the state and the tag of the entry on the bus and does not invalidate the state of the entry.

    Abstract translation: 处理器包括具有多个条目的高速缓冲存储器。 每个条目保存高速缓存行的数据，高速缓存行的状态和高速缓存行的标签。 高速缓存存储器包括包括一个或多个有限状态机的引擎。 处理器还包括到总线的接口，响应于遇到架构回写和无效指令，处理器将经修改的高速缓存行从高速缓冲存储器写回系统存储器。 响应于遇到架构回写和无效指令，处理器也使高速缓冲存储器条目的状态无效。 响应于被指示执行高速缓存诊断操作，对于条目的每个条目，引擎将条目的状态和标签写入总线​​，并且不使条目的状态无效。

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