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    MEMORY SENSE AMPLIFIER TRIMMING
    22.
    发明申请
    MEMORY SENSE AMPLIFIER TRIMMING 有权

    公开(公告)号：US20220093142A1

    公开(公告)日：2022-03-24

    申请号：US17543046

    申请日：2021-12-06

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

    IPC: G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C29/42 ,  G11C11/16

    Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

    Memory sense amplifier trimming
    23.
    发明授权
    Memory sense amplifier trimming 有权

    公开(公告)号：US11227640B2

    公开(公告)日：2022-01-18

    申请号：US16870220

    申请日：2020-05-08

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

    IPC: G11C7/08 ,  G11C7/06 ,  G11C11/16 ,  G11C29/42 ,  G11C7/10

    Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

    PUF METHOD AND STRUCTURE
    24.
    发明申请
    PUF METHOD AND STRUCTURE 有权

    公开(公告)号：US20210409233A1

    公开(公告)日：2021-12-30

    申请号：US17228840

    申请日：2021-04-13

    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

    Inventor： Shih-Lien Linus Lu ,  Saman Adham ,  Yu-Der Chih

    IPC: H04L9/32 ,  G06F21/75 ,  H04L9/08 ,  G06F3/06 ,  G06F12/06

    Abstract: Disclosed herein is related to physical unclonable function (PUF) with enhanced security based on one time programmable (OTP) memory device. In one aspect, indirection process, hashing or a combination of them can be employed to hide a key for allowing access to an integrated circuit. Each indirection process may include identifying a subsequent address of the OTP memory device based on content stored by the OTP memory device at an address, and obtaining subsequent content stored by the OTP memory device at the subsequent address. Through a number of indirection processes, hidden content stored by the OTP memory device can be obtained. In one approach, hashing can be applied to input bits to obtain an address of the OTP memory device to apply. In one approach, hashing can be applied to the hidden content stored by the OTP memory device to generate the key.

    Memory cell array circuit
    25.
    发明授权
    Memory cell array circuit 有权

    公开(公告)号：US11151296B2

    公开(公告)日：2021-10-19

    申请号：US16401486

    申请日：2019-05-02

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    Inventor： Chi-Hsiang Weng ,  Yu-Der Chih

    IPC: H01L29/06 ,  G06F30/39 ,  H01L27/24 ,  H01L27/22 ,  H01L27/115 ,  G11C13/00 ,  H01L45/00 ,  G06F30/392 ,  G06F30/394

    Abstract: A memory cell array includes a first column of memory cells, a second column of memory cells, a first bit line, a second bit line and a source line. The second column of memory cells is separated from the first column of memory cells in a first direction. The first column of memory cells and the second column of memory cells are arranged in a second direction. The first bit line is coupled to the first column of memory cells, and extends in the second direction. The second bit line is coupled to the second column of memory cells, and extends in the second direction. The source line extends in the second direction, is coupled to the first column of memory cells and the second column of memory cells.

    SRAM-based cell for in-memory computing and hybrid computations/storage memory architecture
    30.
    发明授权
    SRAM-based cell for in-memory computing and hybrid computations/storage memory architecture 有权

    公开(公告)号：US12277319B2

    公开(公告)日：2025-04-15

    申请号：US18321615

    申请日：2023-05-22

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Yu-Der Chih ,  Chia-Fu Lee ,  Jonathan Tsung-Yung Chang

    IPC: G06F3/06 ,  G06F7/544 ,  G11C11/419

    Abstract: An in-memory computing device includes in some examples a two-dimensional array of memory cells arranged in rows and columns, each memory cell made of a nine-transistor current-based SRAM. Each memory cell includes a six-transistor SRAM cell and a current source coupled by a switching transistor, which is controlled by input signals on an input line, to an output line associates with the column of memory cells the memory cell is in. The current source includes a switching transistor controlled by the state of the six-transistor SRAM cell, and a current regulating transistor adapted to generate a current at a level determined by a control signal applied at the gate. The control signal can be set such that the total current in each output line is increased by a factor of 2 in each successive column of the memory cells.

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