公开(公告)号：US11227640B2

公开(公告)日：2022-01-18

申请号：US16870220

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

IPC: G11C7/08 ,  G11C7/06 ,  G11C11/16 ,  G11C29/42 ,  G11C7/10

Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

公开(公告)号：US20210409233A1

公开(公告)日：2021-12-30

申请号：US17228840

申请日：2021-04-13

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Shih-Lien Linus Lu ,  Saman Adham ,  Yu-Der Chih

IPC: H04L9/32 ,  G06F21/75 ,  H04L9/08 ,  G06F3/06 ,  G06F12/06

Abstract: Disclosed herein is related to physical unclonable function (PUF) with enhanced security based on one time programmable (OTP) memory device. In one aspect, indirection process, hashing or a combination of them can be employed to hide a key for allowing access to an integrated circuit. Each indirection process may include identifying a subsequent address of the OTP memory device based on content stored by the OTP memory device at an address, and obtaining subsequent content stored by the OTP memory device at the subsequent address. Through a number of indirection processes, hidden content stored by the OTP memory device can be obtained. In one approach, hashing can be applied to input bits to obtain an address of the OTP memory device to apply. In one approach, hashing can be applied to the hidden content stored by the OTP memory device to generate the key.

公开(公告)号：US11151296B2

公开(公告)日：2021-10-19

申请号：US16401486

申请日：2019-05-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chi-Hsiang Weng ,  Yu-Der Chih

IPC: H01L29/06 ,  G06F30/39 ,  H01L27/24 ,  H01L27/22 ,  H01L27/115 ,  G11C13/00 ,  H01L45/00 ,  G06F30/392 ,  G06F30/394

Abstract: A memory cell array includes a first column of memory cells, a second column of memory cells, a first bit line, a second bit line and a source line. The second column of memory cells is separated from the first column of memory cells in a first direction. The first column of memory cells and the second column of memory cells are arranged in a second direction. The first bit line is coupled to the first column of memory cells, and extends in the second direction. The second bit line is coupled to the second column of memory cells, and extends in the second direction. The source line extends in the second direction, is coupled to the first column of memory cells and the second column of memory cells.

公开(公告)号：US11139017B2

公开(公告)日：2021-10-05

申请号：US16810245

申请日：2020-03-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-An Chang ,  Po-Hao Lee ,  Chia-Fu Lee ,  Yi-Chun Shih ,  Yu-Der Chih

IPC: G11C11/16 ,  G11C11/4074 ,  G11C5/14

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a functional device including a selection device; and a bias generator circuit coupled to the selection device and configured to detect a leakage current of the functional device and generate a bias voltage based on the detected leakage current. The bias voltage is provided to the selection device to control the selection device.

公开(公告)号：US11081155B2

公开(公告)日：2021-08-03

申请号：US16431158

申请日：2019-06-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Po-Hao Lee ,  Ku-Feng Lin ,  Yi-Chun Shih ,  Yu-Der Chih

IPC: G11C11/16 ,  H01L43/08 ,  H01L27/22

Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

公开(公告)号：US09865601B2

公开(公告)日：2018-01-09

申请号：US14971461

申请日：2015-12-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kai-Chun Lin ,  Yu-Der Chih ,  Chia-Fu Lee

IPC: H01L27/11 ,  H01L27/105 ,  H01L27/02

CPC classification number: H01L27/1052 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11206 ,  H01L27/228 ,  H01L27/2436

Abstract: The present disclosure relates to a semiconductor integrated circuit. The semiconductor integrated circuit includes a substrate, a first transistor and a first patterned conductive layer. The first transistor has a source region, a drain region in the substrate and a gate region on the substrate. The first patterned conductive layer is electrically connected to the drain region of the first transistor. The first patterned conductive layer includes a first section, a second section and a fusible device.

公开(公告)号：US09767878B1

公开(公告)日：2017-09-19

申请号：US15174614

申请日：2016-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu-Der Chih ,  Tien-Wei Chiang ,  Chun-Jung Lin ,  Harry-Hak-Lay Chuang ,  William J. Gallagher

IPC: G11C11/00 ,  G11C11/16 ,  H01L43/10 ,  H01L43/08

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673

Abstract: A method for controlling a magnetic memory device is provided. The method includes: applying a first control signal and a second control signal to a ferromagnetic fixed layer and a ferromagnetic free layer of the magnetic memory device respectively, wherein a first voltage level of the first control signal is lower than a second voltage level of the second control signal; sensing a first current signal flowing through the magnetic memory device; and determining a logical state of a first data bit according to the first current signal.

公开(公告)号：US12211579B2

公开(公告)日：2025-01-28

申请号：US18424164

申请日：2024-01-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

IPC: G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C11/16 ,  G11C29/42

Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

公开(公告)号：US12176063B2

公开(公告)日：2024-12-24

申请号：US17884650

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih ,  Jonathan Tsung-Yung Chang

IPC: G11C7/12 ,  G11C5/06 ,  G11C7/10 ,  G11C16/04 ,  G11C16/30

Abstract: Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.

公开(公告)号：US20240412785A1

公开(公告)日：2024-12-12

申请号：US18331570

申请日：2023-06-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Cheng Chou ,  Yu-Der Chih

IPC: G11C13/00

Abstract: A memory device includes a first memory array including a plurality of first memory bits. Each of the plurality of first memory bits is configured as a one-time-programmable (OTP) memory bit. A second memory array includes a plurality of second memory bits, each of the plurality of second memory bits being configured as a multi-time-programmable (MTP) memory bit. A lock bit circuit operatively coupled to the first memory array and not the second memory array. The lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been programmed.