公开(公告)号：US20200035804A1

公开(公告)日：2020-01-30

申请号：US16047038

申请日：2018-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor structure includes a semiconductor substrate, a gate structure, a first gate spacer, an interlayer dielectric layer, a contact stop layer, and an air gap. The gate structure is disposed over the semiconductor substrate. The first gate spacer covers a first sidewall of the gate structure. The interlayer dielectric layer is adjacent to the first gate spacer. The contact stop layer is positioned over the first gate spacer and the interlayer dielectric layer. The air gap is between the first gate spacer and the interlayer dielectric layer. The contact stop layer includes a capping portion that seals a top of the air gap.

公开(公告)号：US20190252496A1

公开(公告)日：2019-08-15

申请号：US16396609

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han LIN

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/768

CPC classification number: H01L29/0847 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a first and a second gate stacks disposed over a substrate, having spacers along sidewalls, respectively. The device also includes a source/drain (S/D) feature, a capping layer disposed along upper portions of the spacers, respectively and a dielectric layer along lower portions of the spacers, respectively. The dielectric layer physically contacts the capping layer and a top surface of the dielectric layer is above a top surface of the S/D feature. The device also includes a contact disposed over the S/D feature interfacing the capping layer and dielectric layer.

公开(公告)号：US20190252383A1

公开(公告)日：2019-08-15

申请号：US16391173

申请日：2019-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Han LIN

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/8238 ,  H01L27/088

CPC classification number: H01L27/0924 ,  H01L21/32137 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0886 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device includes first and second Fin FETs and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending in a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending in the second direction. When viewed from above, an end shape the separation plug has a concave curved shape, while an end of the first gate electrode abutting the separation plug has a convex curved shape.

公开(公告)号：US20180358466A1

公开(公告)日：2018-12-13

申请号：US16042164

申请日：2018-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L29/417 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/28247 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate. The semiconductor device also includes a protection element over the gate stack, and a top and a bottom of the protection element have different widths. The semiconductor device further includes a spacer over a side surface of the protection element and a sidewall of the gate stack. In addition, the semiconductor device includes a conductive contact electrically connected to a conductive feature over the semiconductor substrate.

公开(公告)号：US20180174957A1

公开(公告)日：2018-06-21

申请号：US15895895

申请日：2018-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522

Abstract: A method includes depositing a dielectric structure on a first conductive structure, etching the dielectric structure to form a via opening, etching the dielectric structure to form a trench over the via opening, depositing a first protective layer on a bottom surface of the trench, filling the trench and the via opening with a second conductive structure, and removing the first protective layer to form an air gap between the second conductive structure and the dielectric structure.

公开(公告)号：US20180033698A1

公开(公告)日：2018-02-01

申请号：US15727626

申请日：2017-10-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Wei-Ting CHEN

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.

公开(公告)号：US20180019128A1

公开(公告)日：2018-01-18

申请号：US15715762

申请日：2017-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Po-Chi WU ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L21/225 ,  H01L29/36 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/2253 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a substrate, at least one active semiconductor fin, at least one insulating structure, a gate electrode, and a gate dielectric. The active semiconductor fin is disposed on the substrate. The insulating structure is disposed on the substrate and adjacent to the active semiconductor fin. A top surface of the insulating structure is non-concave and is lower than a top surface of the active semiconductor fin. The gate electrode is disposed over the active semiconductor fin. The gate dielectric is disposed between the gate electrode and the active semiconductor fin.

公开(公告)号：US20170358681A1

公开(公告)日：2017-12-14

申请号：US15687723

申请日：2017-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/423

CPC classification number: H01L29/7856 ,  H01L21/32133 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The gate stack includes a first portion and a second portion adjacent to the fin structure, and the first portion is wider than the second portion.

公开(公告)号：US20170154886A1

公开(公告)日：2017-06-01

申请号：US14954380

申请日：2015-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L27/092 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/32155 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823828 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/66545

Abstract: In a method for manufacturing a semiconductor device, a dummy gate layer and a hard mask layer are sequentially formed on a substrate. A first doped portion is formed in the dummy gate layer, and has an etching selectivity with respect to the other portion of the dummy gate layer. Etching masks are formed on portions of the hard mask layer. The hard mask layer and the dummy gate layer are etched to pattern the first doped portion and the other portion of the dummy gate layer into first dummy gates and second dummy gates. The first dummy gates and the second dummy gates have different widths. A dielectric layer is formed to peripherally enclose each of the first dummy gates and each of the second dummy gates. The first dummy gates and the second dummy gates are replaced with first metal gates and second metal gates.

公开(公告)号：US20170141108A1

公开(公告)日：2017-05-18

申请号：US15414413

申请日：2017-01-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/764 ,  H01L21/823431 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor fin, a second semiconductor fin, an air gap and a dielectric cap layer. The first semiconductor fin is disposed on the semiconductor substrate, and the second semiconductor fin is disposed on the semiconductor substrate. The air gap is located between the first semiconductor fin and the second semiconductor fin, and the dielectric cap layer caps a top of the air gap.