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    Nonvolatile memory device and method of programming the same
    22.
    发明授权
    Nonvolatile memory device and method of programming the same 有权
    非易失存储器件及其编程方法

    公开(公告)号：US09564229B2

    公开(公告)日：2017-02-07

    申请号：US15229158

    申请日：2016-08-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoon-Hee Choi ,  Sang-Wan Nam ,  Kang-Bin Lee

    IPC: G11C11/34 ,  G11C16/10 ,  G11C16/04 ,  G11C11/56 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C7/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3459

    Abstract: In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time, wherein the program loop includes a programming step for programming selected memory cells among the memory cells and a verifying step for verifying whether the selected memory cells are program-passed or not. In the programming the selected memory cells, a level of a voltage being applied to a common source line connected to the strings in common may be changed. Thus, in a program operation, power consumption which is needed to charge-discharge the common source line can be decreased while increasing boosting efficiency.

    Abstract translation: 在编程三维非易失性存储器件的方法中，程序循环至少执行一次，其中程序循环包括编程步骤，用于对存储器单元之间选择的存储单元进行编程，以及验证步骤，用于验证所选择的存储器 单元格是否通过程序传递。 在对所选存储单元的编程中，可以改变施加到共同连接到串的公共源极线的电压电平。 因此，在程序运行中，能够提高提升效率的同时，能够减小对公共源极线进行充放电所需要的功耗。

    MEMORY DEVICES HAVING BUILT-IN POWER SUPPORTING CONTROL CIRCUITS THAT PROVIDE INCREASED PROGRAM AND READ RELIABILITY
    24.
    发明申请
    MEMORY DEVICES HAVING BUILT-IN POWER SUPPORTING CONTROL CIRCUITS THAT PROVIDE INCREASED PROGRAM AND READ RELIABILITY 有权

    公开(公告)号：US20250124983A1

    公开(公告)日：2025-04-17

    申请号：US18637829

    申请日：2024-04-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwanghoe Heo ,  Seongjin Kim ,  Sang-Wan Nam

    IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

    Abstract: A memory device includes an array of nonvolatile memory cells and a wordline voltage generator configured to drive: a selected word line within the array with a program voltage, a word line extending immediately adjacent the selected word line with a first voltage during the program operation, and an unselected word line within the array with a second voltage having a magnitude less than a magnitude of the first voltage, during a memory cell program operation. A control block is provided, which drives the wordline voltage generator with a first internal power signal having a first magnitude, in response to a first external supply power signal, drives the wordline voltage generator with a second internal power signal having a second magnitude less than the first magnitude, and selectively redirects power from the first external supply power signal to the second internal power signal, in response to detecting a reduction in current and/or voltage associated with the second external power signal that exceeds a threshold amount.

    Nonvolatile memory device with multiple clocks
    26.
    发明授权
    Nonvolatile memory device with multiple clocks 有权

    公开(公告)号：US12125544B2

    公开(公告)日：2024-10-22

    申请号：US17871358

    申请日：2022-07-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： You-Se Kim ,  Sang-Wan Nam ,  Kee Ho Jung

    IPC: G11C16/32 ,  G11C16/04 ,  G11C16/14 ,  G11C16/24

    CPC classification number: G11C16/32 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/24

    Abstract: A nonvolatile memory device includes: a memory cell array including three or more planes; a first clock generator generating a first clock signal having a first period; a second clock generator generating a second clock signal having a second period that varies with the temperature; a plurality of clock switching controllers outputting one of the first and second clock signals as a reference clock signal; a control logic including a plurality of bitline shutoff generators, which output a plurality of bitline shutoff signals based on the reference clock signal; and a plurality of page buffers connecting bitlines of the planes and data latch nodes in accordance with the bitline shutoff signals.

    Operation method of nonvolatile memory device
    28.
    发明授权
    Operation method of nonvolatile memory device 有权

    公开(公告)号：US11532365B2

    公开(公告)日：2022-12-20

    申请号：US17377141

    申请日：2021-07-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Duk Yu ,  Sang-Wan Nam ,  Jonghoon Park ,  Ho-Jun Lee

    IPC: G11C16/08 ,  G11C16/26 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C16/04

    Abstract: An operation method of a nonvolatile memory device includes receiving a read command and an address, increasing a voltage applied to an unselected word line from an off voltage to a read pass voltage during a setup phase in response to the read command, increasing a voltage applied to an unselected string selection line from the off voltage to a pre-pulse voltage during a first setup phase of the setup phase, increasing a voltage applied to an unselected ground selection line from the off voltage to the pre-pulse voltage during the first setup phase, applying a read voltage to a selected word line to read data corresponding to the address, during a sensing phase following the setup phase, and outputting the read data through data lines after the sensing phase. During the setup phase, a slope of the voltage applied to the unselected word line is varied.

    Non-volatile memory devices and program methods thereof
    29.
    发明授权
    Non-volatile memory devices and program methods thereof 有权

    公开(公告)号：US11367493B2

    公开(公告)日：2022-06-21

    申请号：US16991443

    申请日：2020-08-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wandong Kim ,  Jinwoo Park ,  Seongjin Kim ,  Sang-Wan Nam

    IPC: G11C16/06 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C7/10 ,  G11C16/04 ,  G11C7/04 ,  G11C16/30

    Abstract: A program method of a non-volatile memory device, the non-volatile memory device including a peripheral circuit region and a memory cell region including a cell substrate and a cell string having memory cells stacked perpendicular to a surface of a cell substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell being connected to a second word line closer to the cell substrate, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.

    Three-dimensional nonvolatile memory and method of performing read operation in the nonvolatile memory
    30.
    发明授权
    Three-dimensional nonvolatile memory and method of performing read operation in the nonvolatile memory 有权

    公开(公告)号：US11222697B2

    公开(公告)日：2022-01-11

    申请号：US17023002

    申请日：2020-09-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Wan Nam ,  Won-Taeck Jung

    IPC: G11C16/06 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24

    Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.

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