公开(公告)号：US12125544B2

公开(公告)日：2024-10-22

申请号：US17871358

申请日：2022-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： You-Se Kim ,  Sang-Wan Nam ,  Kee Ho Jung

IPC: G11C16/32 ,  G11C16/04 ,  G11C16/14 ,  G11C16/24

CPC classification number: G11C16/32 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/24

Abstract: A nonvolatile memory device includes: a memory cell array including three or more planes; a first clock generator generating a first clock signal having a first period; a second clock generator generating a second clock signal having a second period that varies with the temperature; a plurality of clock switching controllers outputting one of the first and second clock signals as a reference clock signal; a control logic including a plurality of bitline shutoff generators, which output a plurality of bitline shutoff signals based on the reference clock signal; and a plurality of page buffers connecting bitlines of the planes and data latch nodes in accordance with the bitline shutoff signals.