公开(公告)号：US09240239B2

公开(公告)日：2016-01-19

申请号：US14610584

申请日：2015-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Hwa Kang ,  Sang-Wan Nam ,  Donghyuk Chae ,  ChiWeon Yoon

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/08 ,  H01L27/115

CPC classification number: G11C16/0483 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/24 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.

公开(公告)号：US09478290B1

公开(公告)日：2016-10-25

申请号：US14938394

申请日：2015-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Kyung-Hwa Kang ,  Dae-Seok Byeon ,  Chi-Weon Yoon

IPC: G11C16/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C7/14 ,  G11C8/14 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device is provided as follows. A memory cell array includes strings including first and second strings. Each string includes a ground selection transistor and cell transistors. First and second ground selection lines are connected to a gate of a first ground selection transistor of the first string and a gate of a second ground selection transistor of the second string, respectively. First and second cell gate lines are connected to a gate of a first cell transistor of the first string and a gate of a second cell transistor of the second string, respectively. A first interconnection unit electrically connects a first portion of the first cell gate line to a first portion of the second cell gate line. A second interconnection unit electrically connects a second portion of the first cell gate line to a second portion of the second cell gate line.

Abstract translation: 如下提供存储器件。 存储单元阵列包括包括第一和第二串的串。 每个串包括接地选择晶体管和单元晶体管。 第一和第二接地选择线分别连接到第一串的第一接地选择晶体管的栅极和第二串的第二接地选择晶体管的栅极。 第一和第二单元栅极线分别连接到第一串的第一单元晶体管的栅极和第二串的第二单元晶体管的栅极。 第一互连单元将第一单元栅极线的第一部分电连接到第二单元栅极线的第一部分。 第二互连单元将第一单元栅极线的第二部分电连接到第二单元栅极线的第二部分。