公开(公告)号：US11101320B2

公开(公告)日：2021-08-24

申请号：US16850691

申请日：2020-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Rwik Sengupta ,  Dharmendar Palle ,  Joon Goo Hong

IPC: G11C11/15 ,  H01L27/22 ,  G11C11/16 ,  G11C13/00 ,  H01F10/32 ,  H01L43/02 ,  H01L27/24

Abstract: A weight cell, an electronic device and a device are provided. The weight cell includes a first resistive memory element and a second resistive memory element, a select transistor, and a layer of Spin Hall (SH) material disposed between the first resistive memory element and the second resistive memory element, the layer of the SH material including a first contact and a second contact. The first contact of the SH material is connected to a drain of the select transistor and the second contact of the SH material is connected to an external word line.

公开(公告)号：US20210118950A1

公开(公告)日：2021-04-22

申请号：US16850691

申请日：2020-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan Hatcher ,  Titash Rakshit ,  Jorge Kittl ,  Rwik Sengupta ,  Dharmendar Palle ,  Joon Goo Hong

IPC: H01L27/22 ,  H01L27/24 ,  G11C11/16 ,  H01L43/02 ,  G11C13/00 ,  H01F10/32

Abstract: A weight cell, an electronic device and a device are provided. The weight cell includes a first resistive memory element and a second resistive memory element, a select transistor, and a layer of Spin Hall (SH) material disposed between the first resistive memory element and the second resistive memory element, the layer of the SH material including a first contact and a second contact. The first contact of the SH material is connected to a drain of the select transistor and the second contact of the SH material is connected to an external word line.

公开(公告)号：US10916513B2

公开(公告)日：2021-02-09

申请号：US16453475

申请日：2019-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Harsono S. Simka ,  Ganesh Hegde ,  Joon Goo Hong ,  Rwik Sengupta ,  Mark S. Rodder

IPC: H01L23/00 ,  H01L23/522 ,  H01L27/02 ,  H04L9/32 ,  H01L23/532 ,  G09C1/00

Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. A first portion of the circuit elements are connected to a first portion of the connective components and are active. A the second portion of the circuit elements are connected to a second portion of the connective components and are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry is indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

公开(公告)号：US10886224B2

公开(公告)日：2021-01-05

申请号：US16561340

申请日：2019-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vassilios Gerousis ,  Rwik Sengupta ,  Joon Goo Hong ,  Kevin Michael Traynor

IPC: H01L23/528 ,  H01L23/522

Abstract: A tap cell configured to enable electrical connection from a buried power rail of an integrated circuit to a power distribution network includes. The tap cell includes a buried power rail layer including VDD and VSS power supply lines, insulating layers and metal layers alternately arranged on the buried power rail layer, a first power supply interconnect in metal layer M1 or higher electrically coupled to the VDD power supply line, and a second power supply interconnect in metal layer M1 or higher electrically connected to the VSS power supply line. The first power supply interconnect and the second power supply interconnect are configured to be electrically connected to the power distribution network, and the VDD and VSS power supply lines are configured to supply power from the power distribution network to the buried power rail of the integrated circuit. The tap cell is free of any active semiconductor devices.

公开(公告)号：US10861950B2

公开(公告)日：2020-12-08

申请号：US16121427

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/118

Abstract: A field effect transistor including a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, a drain contact on the drain region, and recesses in the source and drain contacts substantially aligned with the gate contact. Upper surfaces of the recesses in the source and drain contacts are spaced below an upper surface of the gate by a depth.

公开(公告)号：US20190012593A1

公开(公告)日：2019-01-10

申请号：US15806259

申请日：2017-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/78 ,  H01L29/423

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US10153368B2

公开(公告)日：2018-12-11

申请号：US15656898

申请日：2017-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Rwik Sengupta ,  Chris Bowen

IPC: H03K19/20 ,  H01L29/78 ,  H01L27/11

Abstract: A system of unipolar digital logic. Ferroelectric field effect transistors having channels of a first polarity, are combined, in circuits, with simple field effect transistors having channels of the same polarity, to form logic gates and/or memory cells.

公开(公告)号：US20170110595A1

公开(公告)日：2017-04-20

申请号：US15149722

申请日：2016-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Stephen RODDER ,  Joon Goo HONG ,  Titash RAKSHIT

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/778 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684

Abstract: A Gate-All-Around (GAA) Field Effect Transistor (FET) can include a horizontal nanosheet conductive channel structure having a width in a horizontal direction in the GAA FET, a height that is perpendicular to the horizontal direction, and a length that extends in the horizontal direction, where the width of the horizontal nanosheet conductive channel structure defines a physical channel width of the GAA FET. First and second source/drain regions can be located at opposing ends of the horizontal nanosheet conductive channel structure and a unitary gate material completely surrounding the horizontal nanosheet conductive channel structure.

公开(公告)号：US09570395B1

公开(公告)日：2017-02-14

申请号：US15158500

申请日：2016-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Joon Goo Hong ,  Mark Rodder

IPC: H01L23/02 ,  H01L23/528 ,  H01L23/535 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532 ,  H01L29/06

CPC classification number: H01L23/5286 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/535 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/0665 ,  H01L29/785

Abstract: A semiconductor device includes: a substrate; a power rail on the substrate; an active layer on the substrate and at same layer as the power rail; and a contact electrically connecting the power rail to the active layer. The active layer includes source/drain terminals.

Abstract translation: 半导体器件包括：衬底; 基板上的电源轨; 在基板上并且与电力轨道相同层的有源层; 以及将电源轨电连接到有源层的触点。 有源层包括源极/漏极端子。

公开(公告)号：US20150194427A1

公开(公告)日：2015-07-09

申请号：US14534536

申请日：2014-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Raheel Azmat

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a finFET, a metal routing layer, a first local interconnect layer, and a second local interconnect layer. The finFET may include a channel, a first source/drain region, a second source/drain region, and a gate stack. The metal routing layer may be separated from the finFET in a vertical direction. The first local interconnect layer may include a first local interconnect that contacts a first metal route in the metal routing layer and that electrically connects to the first source/drain region. The second local interconnect layer may include a second local interconnect that contacts a second metal route in the metal routing layer and that electrically connects to the gate stack.

Abstract translation: 提供了半导体器件及其形成方法。 半导体器件可以包括finFET，金属布线层，第一局部互连层和第二局部互连层。 finFET可以包括沟道，第一源极/漏极区域，第二源极/漏极区域和栅极堆叠。 金属布线层可以在垂直方向上与finFET分离。 第一局部互连层可以包括接触金属布线层中的第一金属路径并且电连接到第一源极/漏极区的第一局部互连。 第二局部互连层可以包括接触金属布线层中的第二金属路径并且电连接到栅极堆叠的第二局部互连。